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booktitle = {Electronic System Level Synthesis Conference (ESLsyn), 2015}, | booktitle = {Electronic System Level Synthesis Conference (ESLsyn), 2015}, | ||
title = {evercodeML: | title = {evercodeML: | ||
- | year = {2015}, | + | year = 2015, |
pages = {23-26}, | pages = {23-26}, | ||
abstract = {Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like IP-XACT. However, the available options today still lack advanced parametrization capabilities needed to design complex systems with very heterogeneous IP-cores and module providers. This contribution introduces a formal language for SoC integration that overcomes these limitations.}, | abstract = {Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like IP-XACT. However, the available options today still lack advanced parametrization capabilities needed to design complex systems with very heterogeneous IP-cores and module providers. This contribution introduces a formal language for SoC integration that overcomes these limitations.}, | ||
Línea 61: | Línea 61: | ||
address = "Cusco (Peru)", | address = "Cusco (Peru)", | ||
month = " | month = " | ||
- | year = "2013", | + | year = 2013, |
pages = " | pages = " | ||
isbn = " | isbn = " | ||
Línea 72: | Línea 72: | ||
series = {Lecture Notes in Computer Science}, | series = {Lecture Notes in Computer Science}, | ||
volume = {7606}, | volume = {7606}, | ||
- | year = {2013}, | + | year = 2013, |
pages = {225-234}, | pages = {225-234}, | ||
publisher = {Springer Berlin Heidelberg}, | publisher = {Springer Berlin Heidelberg}, |