module registro_wrz_businout #(parameter M=8,valorinicial=0) 
(input ck,w,r,z, inout[M-1:0] data);
reg [M-1:0] q;
initial
q=valorinicial;
always @(posedge ck)
	if (z)
		q<=0;
	else if (w)
		q <= data;
assign data = r ? q:'bz;
endmodule

module problema10 #(parameter M=8)
(input ck, input ra,rb,rc,wa,wb,wc,za,zb,zc,inout [M-1:0] bus);
registro_wrz_businout #(M,10) A(ck,wa,ra,za,bus);
registro_wrz_businout #(M,20) B(ck,wb,rb,zb,bus);
registro_wrz_businout #(M,30) C(ck,wc,rc,zc,bus);
endmodule