-----------------------------------------------------------------------------
 -- Copyright (C) 2005 IMEC                                                  -
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 -----------------------------------------------------------------------------
 -- File           : tb_mux.vhd
 -----------------------------------------------------------------------------
 -- Description    : testbench for multiplexer
 -- --------------------------------------------------------------------------
 -- Author         : Geert Vanwijnsberghe
 -- Date           : 1/12/2006
 -- Version        : 1.1
 -- Change history : 
 ----------------------------------------------------------------------------- 
 -- This code was developed by Osman Allam during an internship at IMEC, 
 -- in collaboration with Geert Vanwijnsberghe, Tom Tassignon en Steven 
 -- Redant. The purpose of this code is to teach students good VHDL coding
 -- style for writing complex behavioural models.
 -----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity tb_mux is
end entity;

architecture test of tb_mux is

  component mux4xbus
    port (
      inport0 : in std_logic_vector;
      inport1 : in std_logic_vector;
      inport2 : in std_logic_vector;
      inport3 : in std_logic_vector;
      sel : in std_logic_vector (1 downto 0);
      outport : out std_logic_vector);
  end component;
  
  component mux2xbus
    port (
      inport0 : in std_logic_vector;
      inport1 : in std_logic_vector;
      sel     : in std_logic;
      outport : out std_logic_vector);
  end component;

  signal bus0 : std_logic_vector(3 downto 0);
  signal bus1 : std_logic_vector(3 downto 0);
  signal bus2 : std_logic_vector(3 downto 0);
  signal bus3 : std_logic_vector(3 downto 0);    
  signal bus4 : std_logic_vector(3 downto 0);
  signal busi : std_logic_vector(3 downto 0);
  signal busout : std_logic_vector(3 downto 0);  
  signal sel1 : std_logic;
  signal sel2 : std_logic_vector(1 downto 0);
    
    
begin
 
  U1 : mux2xbus
  port map(
    inport0 => busi,
    inport1 => bus4,
    sel     => sel1,
    outport => busout
  );
  
  U2 : mux4xbus
  port map(
    inport0 =>bus0,
    inport1 =>bus1,
    inport2 =>bus2,
    inport3 =>bus3,
    sel     =>sel2,
    outport =>busi
  );

  main: process
  begin
    bus0 <= "0000";
    bus1 <= "0001";
    bus2 <= "0010";
    bus3 <= "0100";
    bus4 <= "1000";
    sel1 <= '0';
    sel2 <= "00";
    wait for 10 ns;
    sel1 <= '1';
    wait for 10 ns;
    sel2 <= "00";
    wait for 10 ns;
    sel2 <= "01";
    wait for 10 ns;
    sel2 <= "10";
    wait for 10 ns;
    sel2 <= "11";    
    wait for 10 ns;
    sel1 <= '0';
    wait for 10 ns;
    sel2 <= "00";
    wait for 10 ns;
    sel2 <= "01";
    wait for 10 ns;
    sel2 <= "10";
    wait for 10 ns;
    sel2 <= "11"; 
    wait for 10 ns;
    bus3 <= "1111";
    wait for 10 ns;
    wait;
  end process main;   
   
end architecture;