-----------------------------------------------------------------------------
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-- -----------------------------------------------------------------------------
-- Project     : Micro6 microprocessor
-- Author      : Geert Vanwijnsberghe
-- File        : tb_system.vhd
-- Design      : testbench for system
--------------------------------------------------------------------------------
-- Description : test of memory
-- -----------------------------------------------------------------------------
-- History :
--  13/12/06 : vwb : generation
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity tb_system is
end entity;

architecture test of tb_system is
  signal clk          : std_logic;
  signal rst          : std_logic;
  
  signal EndOfSim    : boolean := false;
  constant clkPeriod : time := 10 ns;
  constant dutyCycle : real := 0.5; 

  component system 
  port (
    rst : std_logic;
    clk : std_logic);
  end component;
  
 
begin
  uut: system 
  port map (
    clk   => clk,
    rst   => rst
  );
    
  -- Clock Generation process
  clock: process
  begin
    clk <= '0';
    wait for (1.0 - dutyCycle) * clkPeriod;
    clk <= '1';
    wait for dutyCycle * clkPeriod;
    if EndOfSim then -- The simulation EndOfSims due to event starvation
      wait;
    end if;
  end process; 
  
  main: process
  begin
    -- Initial inputs
    rst <= '1';
    wait for 5* clkPeriod;
    rst <= '0';

    wait;   -- simulation is stopped by a breakpoint that is set when the last instruction "END;" is executed  
  end process;
  
  
end architecture;