HIPER Project

• Title: HIPER: HIgh PERformance Techniques for the Verification and Design of Digital CMOS VLSI.
• Type: Proyecto I+D
• Reference: TEC2007-61802
• Start date: 01-10-2007
• End date: 30-09-2010 (extended to 30-09-2011)
• Executing institution: Universidad de Sevilla
• Funding institution: Ministerio de Educación y Ciencia
• Funds: 212960 Euros
• Responsible: Dr. Jorge Juan Chico
• Team: Manuel J. Bellido Díaz, Dr. Alejandro Millán Calderón, Dr. Paulino Ruiz de Clavijo Vázquez, David Guerrero Martos, Alejandro Muñoz Rivera, Enrique Ostúa Arangüena, Dr. Julián Viejo Cortés, José Ignacio Villar de Ossorno, Juan Quirós Carmona

The finality of this project is to develop the main research line of the applying team, devoted to the design and verification of high performance digital integrated circuits. This line, previously supported by the projects MODEL (TIC2000-1350) and META (TEC2004-00840/MIC) has generated important results and has opened interesting continuation paths that we expect to develop in the framework of the present project. In general terms, the main objectives of this project are:

• As a continuation of the META project, advance in the generation of high accuracy logic-level simulation and current and power estimation tools, by incorporating new behavioral and computational models. Integration of these tools with the design flow to improve the use and diffusion of the tools. Application of the developed capabilities to a variety of problems: differential power analysis (DPA), local power estimation, etc.

• As a new main objective not directly related to the META project, we will devote especial efforts to the exploration of new design techniques for high-performance digital circuits (high speed, low power, etc.). In this sense we will work on three main sub-lines that arise from recent preliminary results obtained in our group:
  • Design of low-power, high-performance logic cells, by using the capabilities of modern technologies: twin and triple-well, variable threshold voltage, etc.
  • Development and evaluation of new skew-tolerant clocking schemes for high speed and low power.
  • The development of methodologies for the analysis, design and validation of advanced arithmetic structures.