Publications

Books and book chapters

"2012" (1)

(“2012”) “Open Development Platform for Embedded Systems”. In “Grid Computing – Technology and Applications, Widespread Coverage and New Horizons”. pp. “311–324”. “InTech, Croatia”. ISBN: “978-953-51-0604-3”. doi bibtex

@INBOOK{ostua12,
   author = "Ostua, E. and Mu\~noz, A. and Ruiz-de-Clavijo, P. and Bellido, M.~J. and Guerrero, D. and Millan, A.",
   title = "Open Development Platform for Embedded Systems",
   editor = "S.~Maad",
   booktitle = "Grid Computing -- Technology and Applications, Widespread Coverage and New Horizons",
   publisher = "InTech, Croatia",
   year = "2012",
   chapter = "14",
   pages = "311--324",
   isbn = "978-953-51-0604-3",
   doi = "10.5772/37739"
   }

"2006" (1)

(“2006”) “Logic-timing Simulation and the Degradation Delay Model”. “Imperial College Press, United Kingdom”. ISBN: “1-86094-589-9”. bibtex

@BOOK{bellido06,
   author = "Bellido, M.~J. and Juan, J. and Valencia, M.",
   title = "Logic-timing Simulation and the Degradation Delay Model",
   publisher = "Imperial College Press, United Kingdom",
   year = "2006",
   isbn = "1-86094-589-9"
   }

"2000" (1)

(“2000”) “Temporización en Circuitos Integrados Digitales CMOS”. “Marcombo, Barcelona (Spain)”. ISBN: “84-267-1246-0”. bibtex

@BOOK{acosta00,
   author = "Acosta, A.~J. and Barriga, A. and Bellido, M.~J. and Juan, J. and Valencia, M.",
   title = "Temporización en Circuitos Integrados Digitales CMOS",
   publisher = "Marcombo, Barcelona (Spain)",
   year = "2000",
   isbn = "84-267-1246-0"
   }

Patents

2018 (1)

(“November” 2018) Dispositivo Electrónico Calculador de Funciones Trigonométricas y Usos del Mismo. P201831133. web bibtex

@misc{guerrero18,
    author = "D. Guerrero and A. Millan and J. Juan and J. Viejo and M.~J. Bellido and P. Ruiz-de-Clavijo  and E. Ostua",
    title = {Dispositivo Electrónico Calculador de Funciones Trigonométricas y Usos del Mismo},
    year = 2018,
    month = "November",
    day = {22},
    note = {P201831133},
    url = {}
}

2016 (1)

(“October” 2016) Circuito Electrónico Digital para el Cálculo de Senos y Cosenos de Múltiplos de un Ángulo. P201600865. web bibtex

@misc{guerrero16,
    author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and J. Viejo and E. Ostua",
    title = {Circuito Electrónico Digital para el Cálculo de Senos y Cosenos de Múltiplos de un Ángulo},
    year = 2016,
    month = "October",
    day = {10},
    note = {P201600865},
    url = {https://www.dte.us.es/id2/lib/exe/fetch.php?media=es:patent:traslado_iet.pdf}
}

Journal papers

2023 (1)

(2023) IRIS: An embedded secure boot for IoT devices. Internet of Things (Netherlands) 23 ISSN: 2542-6605. doi web bibtex

@article{cano-23,
	author = {Cano-Quiveu, G. and Ruiz-de-Clavijo-Vazquez, P. and Bellido, M.J. and Juan-Chico, J. and Viejo-Cortes, J.},
	title = {IRIS: An embedded secure boot for IoT devices},
	year = 2023,
	journal = {Internet of Things (Netherlands)},
	volume = {23},
        issn = 2542-6605,
	doi = {10.1016/j.iot.2023.100874},
	url = {https://www.scopus.com/inward/record.uri?eid=2-s2.0-85165888599&doi=10.1016%2fj.iot.2023.100874&partnerID=40&md5=e031d3651d59c339a13d0a1da9a40630},
	type = {Article}
}

2021 (2)

(2021) “Embedded LUKS (E-LUKS): a hardware solution to IoT security”. “Electronics” 10 (23) pp. 1–22. ISSN: “2079-9292”. doi bibtex

@article{cano21-2,
	author = "G. Cano-Quiveu and P. Ruiz-de-Clavijo-Vazquez and M.J. Bellido-Diaz and J. Juan-Chico and J. Viejo-Cortes and D. Guerrero-Martos and E. Ostua-Aranguena",
	title = "Embedded LUKS (E-LUKS): a hardware solution to IoT security",
	journal = "Electronics",
	volume = 10,
	number = 23,
	year = 2021,
	pages = 1--22,
	issn = "2079-9292",
        doi = 10.3390/electronics10233036
}

(2021) “An Integrated Digital System Design Framework with On-Chip Functional Verification and Performance Evaluation”. “IEEE Access” “9” (“”) pp. “161383–161394”. ISSN: 2169-3536. doi bibtex

@article{cano21-1,
	author = "G. Cano-Quiveu and P. Ruiz-de-Clavijo-Vazquez and M.J. Bellido-Diaz and D. Guerrero-Martos and J. Viejo-Cortes and J. Juan-Chico",
	title = "An Integrated Digital System Design Framework with On-Chip Functional Verification and Performance Evaluation",
	journal = "IEEE Access",
	volume = "9",
	number = "",
	year = 2021,
	pages = "161383--161394",
	issn = 2169-3536,
        doi = 10.1109/ACCESS.2021.3132188
}

2020 (2)

(2020) “Using the complement of the cosine to compute trigonometric functions”. “EURASIP Journal on Advances in Signal Processing” “2020” (“35”) pp. “1–21”. ISSN: 1687-6172. doi bibtex

@article{guerrero20-1,
	author = "D. Guerrero-Martos and A. Millan-Calderon and J. Juan-Chico and J. Viejo-Cortes and M.J. Bellido-Diaz and P. Ruiz-de-Clavijo-Vazquez and E. Ostua-Aranguena",
	title = "Using the complement of the cosine to compute trigonometric functions",
	journal = "EURASIP Journal on Advances in Signal Processing",
	volume = "2020",
	number = "35",
	year = 2020,
	pages = "1--21",
	issn = 1687-6172,
        doi = 10.1186/s13634-020-00692-5
}

(2020) “Address-encoded byte order”. “Microprocessors and Microsystems (MicPro)” “78” pp. “1–9”. ISSN: “0141-9331”. doi bibtex

@article{guerrero20-2,
	author = "D. Guerrero-Martos and G. Cano-Quiveu and J. Juan-Chico and A. Millan-Calderon and M.J. Bellido-Diaz and J. Viejo-Cortes and P. Ruiz-de-Clavijo-Vazquez and E. Ostua-Aranguena",
	title = "Address-encoded byte order",
	journal = "Microprocessors and Microsystems (MicPro)",
	volume = "78",
	year = 2020,
	pages = "1--9",
	issn = "0141-9331",
        doi = 10.1016/j.micpro.2020.103268
}

2019 (1)

(2019) “High-Performance Time Server Core for FPGA System-on-Chip”. “Electronics” “8” (“5”) pp. “1–28”. ISSN: “2079-9292”. doi bibtex

@article{viejo19,
	author = "J. Viejo and J. Juan and M. J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and G. Cano",
	title = "High-Performance Time Server Core for FPGA System-on-Chip",
	journal = "Electronics",
	volume = "8",
	number = "5",
	year = 2019,
	pages = "1--28",
	issn = "2079-9292",
        doi = "10.3390/electronics8050528"
}

2017 (1)

(2017) “Minimalistic SDHC-SPI hardware reader module for boot loader applications”. “Microelectronics Journal” “67” (“”) pp. “32–37”. ISSN: “0026-2692”. doi bibtex

@article{clavijo17,
	author = "P. Ruiz-de-Clavijo and E. Ostua and M. J. Bellido and J. Juan and J. Viejo and D. Guerrero",
	title = "Minimalistic SDHC-SPI hardware reader module for boot loader applications",
	journal = "Microelectronics Journal",
	volume = "67",
	number = "",
	year = 2017,
	pages = "32--37",
	issn = "0026-2692",
        doi = "10.1016/j.mejo.2017.07.007"
}

2016 (1)

(2016) “Fast Hardware Implementations of Static P Systems”. “Computing and Informatics” “35” (“3”) pp. “687–718”. ISSN: “1335-9150 ”. bibtex

@article{quiros16,
	author = "J. Quiros and S. Verlan and J. Viejo and A. Millan and M.~J. Bellido",
	title = "Fast Hardware Implementations of Static P Systems",
	journal = "Computing and Informatics",
	volume = "35",
	number = "3",
	year = 2016,
	pages = "687--718",
	issn = "1335-9150 "
}

"2013" (1)

(“2013”) “NanoFS: a hardware-oriented file system”. “Electronics Letters” “49” (“19”) pp. “1216–1218”. “The Institution of Engineering and Technology”. “England”. ISSN: “0013-5194”. doi bibtex

@article{clavijo13,
	author = "P. Ruiz-de-Clavijo and E. Ostua and J. Juan and M. J. Bellido and J. Viejo and D. Guerrero",
	title = "NanoFS: a hardware-oriented file system",
	journal = "Electronics Letters",
	volume = "49",
	number = "19",
	year = "2013",
	pages = "1216--1218",
	publisher = "The Institution of Engineering and Technology",
	address = "England",
	issn = "0013-5194",
	doi = "10.1049/el.2013.1961",
}

"2012" (1)

(“2012”) “Long-term on-chip verification of systems with logical events scattered in time”. “Microprocessors and Microsystems” “36” (“5”) pp. “402–408”. “Elsevier”. “United Kingdom”. ISSN: “0141-9331”. doi bibtex

@article{viejo12,
	author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and E. Ostua and J. Quiros",
	title = "Long-term on-chip verification of systems with logical events scattered in time",
	journal = "Microprocessors and Microsystems",
	volume = "36",
	number = "5",
	year = "2012",
	pages = "402--408",
	publisher = "Elsevier",
	address = "United Kingdom",
	issn = "0141-9331",
	doi = "10.1016/j.micpro.2012.02.005",
}

"2011" (2)

(“2011”) “Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation”. “IEEE Transactions on Instrumentation and Measurement” “60” (“12”) pp. “3961–3963”. “IEEE Press”. “United States of America”. ISSN: “0018-9456”. doi bibtex

@article{viejo11,
	author = "J. Viejo and J. Juan and M. J. Bellido and A. Millan and P. Ruiz-de-Clavijo",
	title = "Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation",
	journal = "IEEE Transactions on Instrumentation and Measurement",
	volume = "60",
	number = "12",
	year = "2011",
	pages = "3961--3963",
	publisher = "IEEE Press",
	address = "United States of America",
	issn = "0018-9456",
	doi = "10.1109/TIM.2011.2164828"
}

(“2011”) “Studying the viability of static CMOS gates with a large number of inputs when using separate transistor wells”. “Journal of Low Power Electronics” “7” (“3”) pp. “444–452”. “American Scientific Publishers”. “United States of America”. ISSN: “1546-1998”. doi bibtex

@article{guerrero11,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Studying the viability of static CMOS gates with a large number of inputs when using separate transistor wells",
	journal = "Journal of Low Power Electronics",
	volume = "7",
	number = "3",
	year = "2011",
	pages = "444--452", 
	publisher = "American Scientific Publishers",
	address = "United States of America",
	issn = "1546-1998",
	doi = "10.1166/jolpe.2011.1145"
}

"2010" (1)

(“2010”) “Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies”. “Journal of Low Power Electronics” “6” (“1”) pp. “93–102”. “American Scientific Publishers”. “United States of America”. ISSN: “1546-1998”. doi bibtex

@article{millan10,
	author = "A. Millan and M.~J. Bellido and J. Juan and D. Guerrero and P. Ruiz-de-Clavijo and J. Viejo",
	title = "Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies",
	journal = "Journal of Low Power Electronics",
	volume = "6",
	number = "1",
	year = "2010",
	pages = "93--102",
	publisher = "American Scientific Publishers",
	address = "United States of America",
	issn = "1546-1998",
	doi = "10.1166/jolpe.2010.1059"
}

"2007" (1)

(“2007”) “Improving the performance of static CMOS gates by using independent bodies”. “Journal of Low Power Electronics” “3” (“1”) pp. “70–77”. “American Scientific Publishers”. “United States of America”. ISSN: “1546-1998”. doi bibtex

@article{guerrero07,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Improving the performance of static CMOS gates by using independent bodies",
	journal = "Journal of Low Power Electronics",
	volume = "3",
	number = "1",
	year = "2007",
	pages = "70--77",
	publisher = "American Scientific Publishers",
	address = "United States of America",
	issn = "1546-1998",
	doi = "10.1166/jolpe.2007.120"
}

"2006" (2)

(“2006”) “Automated performance evaluation of skew-tolerant clocking schemes”. “International Journal of Electronics” “93” (“12”) pp. “819–842”. “Taylor & Francis”. “United Kingdom”. ISSN: “0020-7217”. doi bibtex

@article{guerrero06,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Automated performance evaluation of skew-tolerant clocking schemes",
	journal = "International Journal of Electronics",
	volume = "93",
	number = "12",
	year = "2006",
	pages = "819--842",
	publisher = "Taylor & Francis",
	address = "United Kingdom",
	issn = "0020-7217",
	doi = "10.1080/00207210500347410"
}

(“2006”) “Accurate logic-level current estimation for digital CMOS circuits”. “Journal of Low Power Electronics” “2” (“”) pp. “87–94”. “American Scientific Publishers”. “United States of America”. ISSN: “1546-1998”. doi bibtex

@article{clavijo06,
	author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua and J. Viejo",
	title = "Accurate logic-level current estimation for digital CMOS circuits",
	journal = "Journal of Low Power Electronics",
	volume = "2",
	number = "",
	year = "2006",
	pages = "87--94",
	publisher = "American Scientific Publishers",
	address = "United States of America",
	issn = "1546-1998",
	doi = "10.1166/jolpe.2006.010"
}

"2001" (1)

(“2001”) “Switching activity evaluation of CMOS digital circuits using logic timing simulation”. “IEE Electronics Letters” “37” (“9”) pp. “555–557”. “IEE”. “United Kingdom of Great Britain and Northern Ireland”. ISSN: “0013-5194”. doi bibtex

@article{juan01,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C. Baena and C.~J. Jimenez and M. Valencia",
	title = "Switching activity evaluation of CMOS digital circuits using logic timing simulation",
	journal = "IEE Electronics Letters",
	volume = "37",
	number = "9",
	year = "2001",
	pages = "555--557",
	publisher = "IEE",
	address = "United Kingdom of Great Britain and Northern Ireland",
	issn = "0013-5194",
	doi = "10.1049/el:20010389"
}

"2000" (1)

(“2000”) “Logical modelling of delay degradation effect in static CMOS gates”. “IEE Proceedings on Circuits Devices Systems Engineering” “147” (“2”) pp. “107–117”. “IEE”. “United Kingdom of Great Britain and Northern Ireland”. ISSN: “1350-2409”. doi bibtex

@article{bellido00,
	author = "M.~J. Bellido and J. Juan and A.~J. Acosta and M. Valencia and J.~L. Huertas",
	title = "Logical modelling of delay degradation effect in static CMOS gates",
	journal = "IEE Proceedings on Circuits Devices Systems Engineering",
	volume = "147",
	number = "2",
	year = "2000",
	pages = "107--117",
	publisher = "IEE",
	address = "United Kingdom of Great Britain and Northern Ireland", 
	issn = "1350-2409",
	doi = "10.1049/ip-cds:20000197"
}

Conference papers

2015 (1)

(June 2015) evercodeML: A formal language for SoC integration. In Electronic System Level Synthesis Conference (ESLsyn), 2015. pp. 23-26. ISBN: 979-10-92279-13-9. ISSN: 2117-4628. web

Abstract bibtex

@INPROCEEDINGS{7365121,
    author = {J. I. Villar and J. Juan and D. Guerrero and M. J. Bellido and J. Viejo},
    booktitle = {Electronic System Level Synthesis Conference (ESLsyn), 2015},
    title = {evercodeML: A formal language for SoC integration},
    year = 2015,
    pages = {23-26},
    abstract = {Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like IP-XACT. However, the available options today still lack advanced parametrization capabilities needed to design complex systems with very heterogeneous IP-cores and module providers. This contribution introduces a formal language for SoC integration that overcomes these limitations.},
    keywords = {formal languages;logic design;system-on-chip;IP-XACT;SoC integration;complex SoC design;evercodeML;formal language;heterogeneous IP-cores;module description languages;module providers;system integration;Field programmable gate arrays;Generators;Hardware;Hardware design languages;Packaging;System integration;XML;FPGA;IP-XACT;IP-core;SoC},
    issn = {2117-4628},
    isbn = {979-10-92279-13-9},
    url = {http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7365121},
    month = {June}
}

2013 (2)

(“February” 2013) “XML-based Description Language for Heterogeneous and Highly-configurable IP-core Integration”. In “Proc. 19th Iberchip Workshop (IWS)”. pp. “–”. “Cusco (Peru)”. ISBN: “978-1-4673-4899-7”. bibtex

@inproceedings{villar13,
	author = "J.~I. Villar and J. Juan and M.~J. Bellido and J. Viejo",
	title = "XML-based Description Language for Heterogeneous and Highly-configurable IP-core Integration",
	booktitle = "Proc. 19th Iberchip Workshop (IWS)",
	address = "Cusco (Peru)",
	month = "February",
	year = 2013,
	pages = "--", 
	isbn = "978-1-4673-4899-7"
}

(2013) Network Time Synchronization: A Full Hardware Approach. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Lecture Notes in Computer Science 7606 pp. 225-234. Springer Berlin Heidelberg. ISBN: 978-3-642-36156-2. doi web bibtex

@inproceedings{juan13,
	author = "J. Juan and J. Viejo and M.~J. Bellido",
	title = {Network Time Synchronization: A Full Hardware Approach},
	booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation},
	series = {Lecture Notes in Computer Science},
	volume = {7606},
	year = 2013,
	pages = {225-234},
	publisher = {Springer Berlin Heidelberg},
	isbn = {978-3-642-36156-2},
	doi = {10.1007/978-3-642-36157-9_23},
	editor = {Ayala, JoséL. and Shang, Delong and Yakovlev, Alex},
	url = {http://dx.doi.org/10.1007/978-3-642-36157-9_23},
	keywords = {digital systems; hardware; network time synchronization; FPGA}
}

"2018" (1)

(“September” “2018”) “OpenRISC hardware bootloader over WiFi”. In “The open source digital design conference (ORConf)”. pp. “”. “Gdansk (Poland)”. bibtex

@inproceedings{cano18,
	author = "G. Cano-Quiveu",
	title = "OpenRISC hardware bootloader over WiFi",
	booktitle = "The open source digital design conference (ORConf)",
	address = "Gdansk (Poland)",
	month = "September",
	year = "2018",
	pages = ""
}

"2016" (2)

(“February” “2016”) “Case study: performance and power analysis of a dynamically reconfigurable hardware/software cryptosystem”. In “Proc. 22th Iberchip Workshop (IWS)”. pp. “112–115”. “Florianopolis (Brazil)”. bibtex

@inproceedings{fayula16,
	author = "M. Fayula and J. Juan and J. Viejo",
	title = "Case study: performance and power analysis of a dynamically reconfigurable hardware/software cryptosystem",
	booktitle = "Proc. 22th Iberchip Workshop (IWS)",
	address = "Florianopolis (Brazil)",
	month = "February",
	year = "2016",
	pages = "112--115"
}

(“February” “2016”) “Building a basic membrane computer”. In “Proc. 14th Brainstorming Week on Membrane Computing (BWMC)”. pp. “269–280”. “Universidad de Sevilla, Sevilla (Spain)”. bibtex

@inproceedings{millan16,
	author = "A. Millan and J. Viejo and J. Quiros and M. J. Bellido and D. Guerrero and E. Ostua",
	title = "Building a basic membrane computer",
	booktitle = "Proc. 14th Brainstorming Week on Membrane Computing (BWMC)",
	address = "Universidad de Sevilla, Sevilla (Spain)",
	month = "February",
	year = "2016",
	pages = "269--280"
}

"2013" (1)

(“2013”) “Fast Hardware Implementations of P Systems”. In “Membrane Computing”. Lecture Notes in Computer Science 7762 pp. 404-423. Springer Berlin Heidelberg. ISBN: 978-3-642-36750-2. doi web bibtex

@inproceedings{verlan13,
	author = "S. Verlan and J. Quiros",
	title = "Fast Hardware Implementations of P Systems",
	booktitle = "Membrane Computing",
	series = {Lecture Notes in Computer Science},
	volume={7762},
	year = "2013",
	pages = {404-423},
	publisher={Springer Berlin Heidelberg},
	isbn={978-3-642-36750-2},
	doi={10.1007/978-3-642-36751-9_27},
	editor={Csuhaj-Varjú, Erzsébet and Gheorghe, Marian and Rozenberg, Grzegorz and Salomaa, Arto and Vaszil, György},
	url={http://dx.doi.org/10.1007/978-3-642-36751-9_27}
}

"2012" (1)

(“September” “2012”) “Diseño e implementación de un controlador domótico reconfigurable basado en hardware y software libre”. In “Proc. 12th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “161–166”. “Elche (Spain)”. ISBN: “978-84-695-4470-9”. bibtex

@inproceedings{ruiz12,
	author = "J. Ruiz and J.~I. Villar and M.~J. Bellido and D. Guerrero and J. Viejo and P. Ruiz-de-Clavijo and J. Juan",
	title = "Diseño e implementación de un controlador domótico reconfigurable basado en hardware y software libre",
	booktitle = "Proc. 12th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Elche (Spain)",
	month = "September",
	year = "2012",
	pages = "161--166", 
	isbn = "978-84-695-4470-9"
}

"2011" (2)

(“April” “2011”) “Implementation of a configuration server for a hardware SNTP synchronization platform based on FPGA”. In “Proc. 7th Southern Conference on Programmable Logic (SPL)”. pp. “239–244”. “Cordoba (Argentina)”. ISBN: “978-1-4244-8846-9”. bibtex

@inproceedings{quiros11,
	author = "J. Quiros and J. Viejo and A. Millan and A. Mu\~noz and J.~I. Villar and D. Guerrero",
	title = "Implementation of a configuration server for a hardware SNTP synchronization platform based on FPGA",
	booktitle = "Proc. 7th Southern Conference on Programmable Logic (SPL)",
	address = "Cordoba (Argentina)",
	month = "April",
	year = "2011",
	pages = "239--244", 
	isbn = "978-1-4244-8846-9"
}

(“April” “2011”) “Python as a Hardware Description Language: A Case Study”. In “Proc. 7th Southern Conference on Programmable Logic (SPL)”. pp. “117–122”. “Cordoba (Argentina)”. ISBN: “978-1-4244-8846-9”. bibtex

@inproceedings{villar11,
	author = "J.~I. Villar and J. Juan and M.~J. Bellido and J. Viejo and D. Guerrero and J. Decaluwe",
	title = "Python as a Hardware Description Language: A Case Study",
	booktitle = "Proc. 7th Southern Conference on Programmable Logic (SPL)",
	address = "Cordoba (Argentina)",
	month = "April",
	year = "2011",
	pages = "117--122", 
	isbn = "978-1-4244-8846-9"
}

"2010" (4)

(“November” “2010”) “Long-term on-chip verification of systems with logical events scattered in time”. In “Proc. 25th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “323–326”. “Lanzarote (Spain)”. ISBN: “978-84-693-7393-4”. bibtex

@inproceedings{viejo10-3,
	author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and E. Ostua and J. Quiros",
	title = "Long-term on-chip verification of systems with logical events scattered in time",
	booktitle = "Proc. 25th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Lanzarote (Spain)",
	month = "November",
	year = "2010",
	pages = "323--326", 
	isbn = "978-84-693-7393-4"
}

(“September” “2010”) “Verificación on-chip de larga duración de sistemas con eventos lógicos dispersos en el tiempo”. In “Proc. 10th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “269–276”. “Valencia (Spain)”. ISBN: “978-84-92812-56-1”. bibtex

@inproceedings{viejo10-2,
	author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and M.~J. Bellido and J. Quiros",
	title = "Verificación on-chip de larga duración de sistemas con eventos lógicos dispersos en el tiempo",
	booktitle = "Proc. 10th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Valencia (Spain)",
	month = "September",
	year = "2010",
	pages = "269--276", 
	isbn = "978-84-92812-56-1"
}

(“July” “2010”) “Design and implementation of a suitable core for on-chip long-term verification”. In “Proc. 5th IEEE International Symposium on Industrial Embedded Systems (SIES)”. pp. “234–237”. “Trento (Italy)”. ISBN: “978-1-4244-5840-0”. bibtex

@inproceedings{viejo10-1,
	author = "J. Viejo and J.~I. Villar and J. Juan and A. Millan and M.~J. Bellido and E. Ostua",
	title = "Design and implementation of a suitable core for on-chip long-term verification",
	booktitle = "Proc. 5th IEEE International Symposium on Industrial Embedded Systems (SIES)",
	address = "Trento (Italy)",
	month = "July",
	year = "2010",
	pages = "234--237", 
	isbn = "978-1-4244-5840-0"
}

(“February” “2010”) “Implementación sobre FPGA de un cliente SNTP usando MicroBlaze”. In “Proc. 16th Iberchip Workshop (IWS)”. pp. “–”. “Iguazu Falls (Brazil)”. bibtex

@inproceedings{quiros10,
	author = "J. Quiros and J. Viejo and A. Mu\~noz and A. Millan and E. Ostua and J.~I. Villar",
	title = "Implementación sobre FPGA de un cliente SNTP usando MicroBlaze",
	booktitle = "Proc. 16th Iberchip Workshop (IWS)",
	address = "Iguazu Falls (Brazil)",
	month = "February",
	year = "2010",
	pages = "--"
}

"2009" (8)

(“September” “2009”) “Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “5349” pp. “389–398”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-95947-2”. doi bibtex

@inproceedings{millan09,
	author = "A. Millan and J. Juan and M.~J. Bellido and D. Guerrero and P. Ruiz-de-Clavijo and J. Viejo",
	title = "Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "5349",
	month = "September",
	year = "2009",
	pages = "389--398",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-95947-2",
	doi = "10.1007/978-3-540-95948-9_39"
}

(“September” “2009”) “Aplicación de Picoblaze como Emulador/Receptor de un GPS en el diseño hardware de un cliente/servidor SNTP”. In “Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “193–202”. “Madrid (Spain)”. ISBN: “978-84-8138-832-9”. bibtex

@inproceedings{ostua09,
	author = "E. Ostua and M.~J. Bellido and J. Viejo and A. Millan and A. Mu\~noz and D. Guerrero",
	title = "Aplicación de Picoblaze como Emulador/Receptor de un GPS en el diseño hardware de un cliente/servidor SNTP",
	booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2009",
	pages = "193--202", 
	isbn = "978-84-8138-832-9"
}

(“September” “2009”) “Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión”. In “Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “359–366”. “Madrid (Spain)”. ISBN: “978-84-8138-832-9”. bibtex

@inproceedings{viejo09-2,
	author = "J. Viejo and J. Juan and E. Ostua and A. Millan and P. Ruiz-de-Clavijo and J.~I. Villar and J. Quiros",
	title = "Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión",
	booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2009",
	pages = "359--366", 
	isbn = "978-84-8138-832-9"
}

(“September” “2009”) “Usando Python como HDL: Estudio comparativo de resultados basado en el desarrollo de un periférico real”. In “Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “33–42”. “Madrid (Spain)”. ISBN: “978-84-8138-832-9”. bibtex

@inproceedings{villar09-2,
	author = "J.~I. Villar and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D.Guerrero and A. Mu\~noz",
	title = "Usando Python como HDL: Estudio comparativo de resultados basado en el desarrollo de un periférico real",
	booktitle = "Proc. 9th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2009",
	pages = "33--42", 
	isbn = "978-84-8138-832-9"
}

(“August” “2009”) “Efficient techniques and methodologies for embedded system design using free hardware and open standards”. In “Proc. 19th International Conference on Field Programmable Logic and Applications (FPL)”. pp. “719–720”. “Prague (Czech Republic)”. ISBN: “978-1-4244-3892-1”. bibtex

@inproceedings{villar09-1,
	author = "J.~I. Villar and J. Juan and M.~J. Bellido",
	title = "Efficient techniques and methodologies for embedded system design using free hardware and open standards",
	booktitle = "Proc. 19th International Conference on Field Programmable Logic and Applications (FPL)",
	address = "Prague (Czech Republic)",
	month = "August",
	year = "2009",
	pages = "719--720", 
	isbn = "978-1-4244-3892-1"
}

(“April” “2009”) “Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies”. In “Proc. 4th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)”. pp. “191–196”. “Cairo (Egypt)”. ISBN: “978-1-4244-4321-5”. bibtex

@inproceedings{guerrero09-2,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua",
	title = "Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies",
	booktitle = "Proc. 4th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)",
	address = "Cairo (Egypt)",
	month = "April",
	year = "2009",
	pages = "191--196", 
	isbn = "978-1-4244-4321-5"
}

(“March” “2009”) “Performance Analysis of Bulk-CMOS Gates Using Separated Wells”. In “Proc. 15th Iberchip Workshop (IWS)”. pp. “54–59”. “Buenos Aires (Argentina)”. bibtex

@inproceedings{guerrero09-1,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua",
	title = "Performance Analysis of Bulk-CMOS Gates Using Separated Wells",
	booktitle = "Proc. 15th Iberchip Workshop (IWS)",
	address = "Buenos Aires (Argentina)",
	month = "March",
	year = "2009",
	pages = "54--59"
}

(“March” “2009”) “Accurate and compact implementation of a hardware SNTP Client”. In “Proc. 15th Iberchip Workshop (IWS)”. pp. “504–509”. “Buenos Aires (Argentina)”. bibtex

@inproceedings{viejo09-1,
	author = "J. Viejo and J. Juan and E. Ostua and M.~J. Bellido and A. Millan and A. Mu\~noz and J.~I. Villar",
	title = "Accurate and compact implementation of a hardware SNTP Client",
	booktitle = "Proc. 15th Iberchip Workshop (IWS)",
	address = "Buenos Aires (Argentina)",
	month = "March",
	year = "2009",
	pages = "504--509"
}

"2008" (8)

(“September” “2008”) “Metodología de Diseño de SoC basada en OpenRisc sobre FPGA con Cores y Herramientas Libres”. In “Proc. 8th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “247–256”. “Madrid (Spain)”. ISBN: “978-84-612-5635-8”. bibtex

@inproceedings{villar08,
	author = "J.~I. Villar and M.~J. Bellido and E. Ostua and D. Guerrero and J. Juan and A. Mu\~noz",
	title = "Metodología de Diseño de SoC basada en OpenRisc sobre FPGA con Cores y Herramientas Libres",
	booktitle = "Proc. 8th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2008",
	pages = "247--256", 
	isbn = "978-84-612-5635-8"
}

(“June” “2008”) “Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution”. In “Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)”. pp. “1727–1732”. “Cambridge (United Kingdom)”. ISBN: “978-1-4244-1666-0”. bibtex

@inproceedings{munoz08,
	author = "A. Mu\~noz and E. Ostua and M.~J. Bellido and A. Millan and J. Juan and D. Guerrero",
	title = "Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution",
	booktitle = "Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)",
	address = "Cambridge (United Kingdom)",
	month = "June",
	year = "2008",
	pages = "1727--1732", 
	isbn = "978-1-4244-1666-0"
}

(“June” “2008”) “Design and implementation of a SNTP client on FPGA”. In “Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)”. pp. “1971–1975”. “Cambridge (United Kingdom)”. ISBN: “978-1-4244-1666-0”. bibtex

@inproceedings{viejo08-2,
	author = "J. Viejo and J. Juan and M.~J. Bellido and E. Ostua and A. Millan and P. Ruiz-de-Clavijo and A. Mu\~noz and D. Guerrero",
	title = "Design and implementation of a SNTP client on FPGA",
	booktitle = "Proc. 2008 IEEE International Symposium on Industrial Electronics (ISIE)",
	address = "Cambridge (United Kingdom)",
	month = "June",
	year = "2008",
	pages = "1971--1975", 
	isbn = "978-1-4244-1666-0"
}

(“May” “2008”) “Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies”. In “Proc. 7th Journées d'études Faible Tension Faible Consommation (FTFC)”. pp. “105–110”. “Louvain-la-Neuve (Belgium)”. bibtex

@inproceedings{guerrero08-2,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo, E.Ostua",
	title = "Delay and Power Consumption of Static Bulk-CMOS Gates Using Independent Bodies",
	booktitle = "Proc. 7th Journées d'études Faible Tension Faible Consommation (FTFC)",
	address = "Louvain-la-Neuve (Belgium)",
	month = "May",
	year = "2008",
	pages = "105--110"
}

(“April” “2008”) “Using Independent Bodies in Bulk-CMOS Gates”. In “Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)”. pp. “221”. “Yokohama (Japan)”. bibtex

@inproceedings{guerrero08-1,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and J. Viejo and A. Mu\~noz",
	title = "Using Independent Bodies in Bulk-CMOS Gates",
	booktitle = "Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)",
	address = "Yokohama (Japan)",
	month = "April",
	year = "2008",
	pages = "221"
}

(“April” “2008”) “Internal Power Dissipation of Static CMOS Gates in UDSM Technologies”. In “Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)”. pp. “127”. “Yokohama (Japan)”. bibtex

@inproceedings{millan08,
	author = "A. Millan and M.~J. Bellido and J. Juan and D. Guerrero and P. Ruiz-de-Clavijo and J. Viejo",
	title = "Internal Power Dissipation of Static CMOS Gates in UDSM Technologies",
	booktitle = "Proc. 11th IEEE Symposium on Low-Power and High-Speed Chips (COOLChips)",
	address = "Yokohama (Japan)",
	month = "April",
	year = "2008",
	pages = "127"
}

(“March” “2008”) “Digital Data Processing Peripheral Design for an Embedded Application Based on the Microblaze Soft Core”. In “Proc. 4th Southern Conference on Programmable Logic (SPL)”. pp. “197–200”. “San Carlos de Bariloche (Argentina)”. ISBN: “978-1-4244-1992-0”. bibtex

@inproceedings{ostua08,
	author = "E. Ostua and J. Viejo and M.~J. Bellido and A. Millan and J. Juan and A. Mu\~noz",
	title = "Digital Data Processing Peripheral Design for an Embedded Application Based on the Microblaze Soft Core",
	booktitle = "Proc. 4th Southern Conference on Programmable Logic (SPL)",
	address = "San Carlos de Bariloche (Argentina)",
	month = "March",
	year = "2008",
	pages = "197--200", 
	isbn = "978-1-4244-1992-0"
}

(“March” “2008”) “Implementation of a FFT/IFFT module on FPGA: Comparison of methodologies”. In “Proc. 4th Southern Conference on Programmable Logic (SPL)”. pp. “7–11”. “San Carlos de Bariloche (Argentina)”. ISBN: “978-1-4244-1992-0”. bibtex

@inproceedings{viejo08-1,
	author = "J. Viejo and A. Millan and M.~J. Bellido and E. Ostua and P. Ruiz-de-Clavijo and A. Mu\~noz",
	title = "Implementation of a FFT/IFFT module on FPGA: Comparison of methodologies",
	booktitle = "Proc. 4th Southern Conference on Programmable Logic (SPL)",
	address = "San Carlos de Bariloche (Argentina)",
	month = "March",
	year = "2008",
	pages = "7--11", 
	isbn = "978-1-4244-1992-0"
}

"2007" (7)

(“November” “2007”) “The effect of using separated bodies over static power consumption in Static Bulk-CMOS gates”. In “Proc. 22th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “181–185”. “Seville (Spain)”. ISBN: “978-84690-8629-2”. bibtex

@inproceedings{guerrero07-4,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "The effect of using separated bodies over static power consumption in Static Bulk-CMOS gates",
	booktitle = "Proc. 22th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Seville (Spain)",
	month = "November",
	year = "2007",
	pages = "181--185", 
	isbn = "978-84690-8629-2"
}

(“September” “2007”) “Static power consumption in CMOS gates using independent bodies”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “4644” pp. “404–412”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-74441-2”. doi bibtex

@inproceedings{guerrero07-3,
	author = "D. Guerrero and A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Static power consumption in CMOS gates using independent bodies",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "4644",
	month = "September",
	year = "2007",
	pages = "404--412",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-74441-2",
	doi = "10.1007/978-3-540-74442-9_39"
}

(“September” “2007”) “Un ejemplo de implantación de una distribución Linux en un SoC basado en hardware libre”. In “Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “85–92”. “Zaragoza (Spain)”. ISBN: “978-84-9732-600-1”. bibtex

@inproceedings{munoz07,
	author = "A. Mu\~noz and E. Ostua and P. Ruiz-de-Clavijo and M.~J. Bellido and J. Viejo and A. Millan and J. Juan and D. Guerrero",
	title = "Un ejemplo de implantación de una distribución Linux en un SoC basado en hardware libre",
	booktitle = "Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Zaragoza (Spain)",
	month = "September",
	year = "2007",
	pages = "85--92", 
	isbn = "978-84-9732-600-1"
}

(“September” “2007”) “Evaluación de metodologías para la implementación de un módulo FFT/IFFT sobre FPGA mediante herramientas a nivel de sistema”. In “Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “205–211”. “Zaragoza (Spain)”. ISBN: “978-84-9732-600-1”. bibtex

@inproceedings{viejo07-2,
	author = "J. Viejo and A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and A. Mu\~noz",
	title = "Evaluación de metodologías para la implementación de un módulo FFT/IFFT sobre FPGA mediante herramientas a nivel de sistema",
	booktitle = "Proc. 7th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Zaragoza (Spain)",
	month = "September",
	year = "2007",
	pages = "205--211", 
	isbn = "978-84-9732-600-1"
}

(“July” “2007”) “Design of a FFT/IFFT module as an IP core suitable for embedded systems”. In “Proc. 2nd IEEE International Symposium on Industrial Embedded Systems (SIES)”. pp. “337–340”. “Lisbon (Portugal)”. ISBN: “1-4244-0840-7”. bibtex

@inproceedings{viejo07-1,
	author = "J. Viejo and A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and A. Mu\~noz",
	title = "Design of a FFT/IFFT module as an IP core suitable for embedded systems",
	booktitle = "Proc. 2nd IEEE International Symposium on Industrial Embedded Systems (SIES)",
	address = "Lisbon (Portugal)",
	month = "July",
	year = "2007",
	pages = "337--340", 
	isbn = "1-4244-0840-7"
}

(“May” “2007”) “Automatic logic synthesis for parallel alternating latches clocking schemes”. In “Proc. Microtechnologies for the New Millennium 2007, SPIE”. pp. “61–69”. “Maspalomas (Spain)”. ISBN: “9780819467188”. bibtex

@inproceedings{guerrero07-2,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Automatic logic synthesis for parallel alternating latches clocking schemes",
	booktitle = "Proc. Microtechnologies for the New Millennium 2007, SPIE",
	address = "Maspalomas (Spain)",
	month = "May",
	year = "2007",
	pages = "61--69", 
	isbn = "9780819467188"
}

(“March” “2007”) “Síntesis lógica automatizada para esquemas de temporización de latches alternantes”. In “Proc. 13th Iberchip Workshop (IWS)”. pp. “349–350”. “Lima (Peru)”. ISBN: “978-9972-242-09-0”. bibtex

@inproceedings{guerrero07-1,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A. Millan and E. Ostua and J. Viejo",
	title = "Síntesis lógica automatizada para esquemas de temporización de latches alternantes",
	booktitle = "Proc. 13th Iberchip Workshop (IWS)",
	address = "Lima (Peru)",
	month = "March",
	year = "2007",
	pages = "349--350", 
	isbn = "978-9972-242-09-0"
}

"2006" (4)

(“November” “2006”) “DSP peripheral on FPGA for electrical networks measurements”. In “Proc. 21th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “–”. “Barcelona (Spain)”. ISBN: “978-84-690-4144-4”. bibtex

@inproceedings{viejo06-3,
	author = "J. Viejo and M.~J. Bellido and A. Millan and E. Ostua and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "DSP peripheral on FPGA for electrical networks measurements",
	booktitle = "Proc. 21th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Barcelona (Spain)",
	month = "November",
	year = "2006",
	pages = "--", 
	isbn = "978-84-690-4144-4"
}

(“October” “2006”) “Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements”. In “Proc. 1st IEEE International Symposium on Industrial Embedded Systems (IES)”. pp. “–”. “Antibes Juan-Les-Pins (France)”. ISBN: “1-4244-0777-X”. bibtex

@inproceedings{viejo06-2,
	author = "J. Viejo and M.~J. Bellido and A. Millan and E. Ostua and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements",
	booktitle = "Proc. 1st IEEE International Symposium on Industrial Embedded Systems (IES)",
	address = "Antibes Juan-Les-Pins (France)",
	month = "October",
	year = "2006",
	pages = "--", 
	isbn = "1-4244-0777-X"
}

(“March” “2006”) “A SOC design methodology for LEON2 on FPGA”. In “Proc. 12th Iberchip Workshop (IWS)”. pp. “242–245”. “San Jose (Costa Rica)”. bibtex

@inproceedings{ostua06,
	author = "E. Ostua and J. Juan and J. Viejo and M.~J. Bellido and D. Guerrero and A. Millan and P. Ruiz-de-Clavijo",
	title = "A SOC design methodology for LEON2 on FPGA",
	booktitle = "Proc. 12th Iberchip Workshop (IWS)",
	address = "San Jose (Costa Rica)",
	month = "March",
	year = "2006",
	pages = "242--245"
}

(“March” “2006”) “Diseño e implementación óptima de periféricos de DSP con System Generator para MicroBlaze”. In “Proc. 12th Iberchip Workshop (IWS)”. pp. “49–52”. “San Jose (Costa Rica)”. bibtex

@inproceedings{viejo06-1,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Diseño e implementación óptima de periféricos de DSP con System Generator para MicroBlaze",
	booktitle = "Proc. 12th Iberchip Workshop (IWS)",
	address = "San Jose (Costa Rica)",
	month = "March",
	year = "2006",
	pages = "49--52"
}

"2005" (10)

(“November” “2005”) “Analysis of internal power consumption in SCMOS gates in submicronic/nanometric technologies”. In “Proc. 20th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “–”. “Lisboa (Portugal)”. ISBN: “972-99387-2-5”. bibtex

@inproceedings{millan05-4,
	author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
	title = "Analysis of internal power consumption in SCMOS gates in submicronic/nanometric technologies",
	booktitle = "Proc. 20th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Lisboa (Portugal)",
	month = "November",
	year = "2005",
	pages = "--", 
	isbn = "972-99387-2-5"
}

(“September” “2005”) “Application of Internode model to global power consumption estimation in SCMOS gates”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “3728” pp. “337–347”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-29013-1”. doi bibtex

@inproceedings{millan05-3,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
	title = "Application of Internode model to global power consumption estimation in SCMOS gates",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "3728",
	month = "September",
	year = "2005",
	pages = "337--347",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-29013-1",
	doi = "10.1007/11556930_35"
}

(“September” “2005”) “Logic-Level Fast Current Simulation for Digital CMOS Circuits”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “3728” pp. “425–435”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-29013-1”. doi bibtex

@inproceedings{clavijo05-2,
	author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua and J. Viejo",
	title = "Logic-Level Fast Current Simulation for Digital CMOS Circuits",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "3728",
	month = "September",
	year = "2005",
	pages = "425--435",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-29013-1",
	doi = "10.1007/11556930_44"
}

(“July” “2005”) “Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies”. In “Proc. PhD Research In Micro-Electronics and Electronics (PRIME)”. pp. “374–377”. “Lausanne (Switzerland)”. ISBN: “0-78039345-7”. bibtex

@inproceedings{millan05-2,
	author = "A. Millan and M.~J. Bellido and J. Juan",
	title = "Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies",
	booktitle = "Proc. PhD Research In Micro-Electronics and Electronics (PRIME)",
	address = "Lausanne (Switzerland)",
	month = "July",
	year = "2005",
	pages = "374--377", 
	isbn = "0-78039345-7"
}

(“July” “2005”) “HALOTIS - High accurate logic timing simulator”. In “Proc. PhD Research In Micro-Electronics and Electronics (PRIME)”. pp. “191–194”. “Lausanne (Switzerland)”. ISBN: “0-78039345-7”. bibtex

@inproceedings{clavijo05-1,
	author = "P. Ruiz-de-Clavijo and M.~J. Bellido and J. Juan",
	title = "HALOTIS - High accurate logic timing simulator",
	booktitle = "Proc. PhD Research In Micro-Electronics and Electronics (PRIME)",
	address = "Lausanne (Switzerland)",
	month = "July",
	year = "2005",
	pages = "191--194", 
	isbn = "0-78039345-7"
}

(“May” “2005”) “Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes”. In “Proc. Microtechnologies for the New Millennium 2005, SPIE”. pp. “467–478”. “Sevilla (Spain)”. ISBN: “9780819458322”. bibtex

@inproceedings{guerrero05-2,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua and J. Viejo",
	title = "Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes",
	booktitle = "Proc. Microtechnologies for the New Millennium 2005, SPIE",
	address = "Sevilla (Spain)",
	month = "May",
	year = "2005",
	pages = "467--478", 
	isbn = "9780819458322"
}

(“March” “2005”) “CMOS digital design techniques for low power and high speed”. In “Proc. Conference on Design, Automation and Test in Europe (DATE)”. pp. “–”. “Munich (Germany)”. ISBN: “0-7695-2288-2”. bibtex

@inproceedings{guerrero05-1,
	author = "D. Guerrero and M.~J. Bellido and J. Juan",
	title = "CMOS digital design techniques for low power and high speed",
	booktitle = "Proc. Conference on Design, Automation and Test in Europe (DATE)",
	address = "Munich (Germany)",
	month = "March",
	year = "2005",
	pages = "--", 
	isbn = "0-7695-2288-2"
}

(“March” “2005”) “Efficient design of a FFT/IFFT-64 module on ASIC”. In “Proc. 11th Iberchip Workshop (IWS)”. pp. “305–306”. “Salvador de Bahia (Brazil)”. ISBN: “959-261-105-X”. bibtex

@inproceedings{millan05-1,
	author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
	title = "Efficient design of a FFT/IFFT-64 module on ASIC",
	booktitle = "Proc. 11th Iberchip Workshop (IWS)",
	address = "Salvador de Bahia (Brazil)",
	month = "March",
	year = "2005",
	pages = "305--306", 
	isbn = "959-261-105-X"
}

(“March” “2005”) “Entorno de desarrollo para SOC basado en el microprocesador LEON2”. In “Proc. 11th Iberchip Workshop (IWS)”. pp. “429–430”. “Salvador de Bahia (Brazil)”. ISBN: “959-261-105-X”. bibtex

@inproceedings{ostua05,
	author = "E. Ostua and J. Viejo and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Entorno de desarrollo para SOC basado en el microprocesador LEON2",
	booktitle = "Proc. 11th Iberchip Workshop (IWS)",
	address = "Salvador de Bahia (Brazil)",
	month = "March",
	year = "2005",
	pages = "429--430", 
	isbn = "959-261-105-X"
}

(“March” “2005”) “Diseño, implementacion y aplicacion a SOC del microprocesador Picoblaze”. In “Proc. 11th Iberchip Workshop (IWS)”. pp. “431–432”. “Salvador de Bahia (Brazil)”. ISBN: “959-261-105-X”. bibtex

@inproceedings{viejo05-1,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Diseño, implementacion y aplicacion a SOC del microprocesador Picoblaze",
	booktitle = "Proc. 11th Iberchip Workshop (IWS)",
	address = "Salvador de Bahia (Brazil)",
	month = "March",
	year = "2005",
	pages = "431--432", 
	isbn = "959-261-105-X"
}

"2004" (2)

(“November” “2004”) “Four phase alternating latches clocking scheme for CMOS sequential circuits”. In “Proc. 19th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “780–783”. “Bordeaux (France)”. ISBN: “2-9522971-0-X”. bibtex

@inproceedings{guerrero04,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and E. Ostua",
	title = "Four phase alternating latches clocking scheme for CMOS sequential circuits",
	booktitle = "Proc. 19th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Bordeaux (France)",
	month = "November",
	year = "2004",
	pages = "780--783", 
	isbn = "2-9522971-0-X"
}

(“September” “2004”) “Signal sampling based transition modeling for digital gates characterization”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “3254” pp. “829–837”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-23095-3”. doi bibtex

@inproceedings{millan04,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
	title = "Signal sampling based transition modeling for digital gates characterization",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "3254",
	month = "September",
	year = "2004",
	pages = "829--837",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-23095-3",
	doi = "10.1007/978-3-540-30205-6_85"
}

"2003" (8)

(“November” “2003”) “Estimation of floating cube delay using transistor path computational delay models for CMOS circuits”. In “Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “95–99”. “Ciudad Real (Spain)”. ISBN: “84-87087-40-X”. bibtex

@inproceedings{guerrero03-2,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and G. Wilke and J.~L. Güntzel",
	title = "Estimation of floating cube delay using transistor path computational delay models for CMOS circuits",
	booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Ciudad Real (Spain)",
	month = "November",
	year = "2003",
	pages = "95--99", 
	isbn = "84-87087-40-X"
}

(“November” “2003”) “Using sampled input signals for SCMOS gates characterization”. In “Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “275–280”. “Ciudad Real (Spain)”. ISBN: “84-87087-40-X”. bibtex

@inproceedings{millan03-1,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
	title = "Using sampled input signals for SCMOS gates characterization",
	booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Ciudad Real (Spain)",
	month = "November",
	year = "2003",
	pages = "275--280", 
	isbn = "84-87087-40-X"
}

(“November” “2003”) “Delay degradation effect in current balanced logic cells”. In “Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “163–165”. “Ciudad Real (Spain)”. ISBN: “84-87087-40-X”. bibtex

@inproceedings{clavijo03,
	author = "P. Ruiz-de-Clavijo and J. Juan and J.~R. Fernandes and M.~J. Bellido and A. Millan and D. Guerrero",
	title = "Delay degradation effect in current balanced logic cells",
	booktitle = "Proc. 18th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Ciudad Real (Spain)",
	month = "November",
	year = "2003",
	pages = "163--165", 
	isbn = "84-87087-40-X"
}

(“September” “2003”) “Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “2799” pp. “501–510”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-20074-1”. doi bibtex

@inproceedings{guerrero03-1,
	author = "D. Guerrero and G. Wilke and J.~L. Guntzel and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A. Millan",
	title = "Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "2799",
	month = "September",
	year = "2003",
	pages = "501--510",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-20074-1",
	doi = "10.1007/978-3-540-39762-5_56"
}

(“September” “2003”) “Diseño eficiente de un módulo FFT/IFFT-64 sobre FPGA”. In “Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “107–114”. “Madrid (Spain)”. ISBN: “84-600-9928-8”. bibtex

@inproceedings{millan03-3,
	author = "A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua",
	title = "Diseño eficiente de un módulo FFT/IFFT-64 sobre FPGA",
	booktitle = "Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2003",
	pages = "107--114", 
	isbn = "84-600-9928-8"
}

(“September” “2003”) “Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de control”. In “Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)”. pp. “385–392”. “Madrid (Spain)”. ISBN: “84-600-9928-8”. bibtex

@inproceedings{ostua03-1,
	author = "E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Barriga and A. Millan and D. Guerrero and J. Juan",
	title = "Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de control",
	booktitle = "Proc. 3rd Jornadas de Computación Reconfigurable y Aplicaciones (JCRA, Workshop on Reconfigurable Computing and Applications)",
	address = "Madrid (Spain)",
	month = "September",
	year = "2003",
	pages = "385--392", 
	isbn = "84-600-9928-8"
}

(“September” “2003”) “Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de Control”. In “Proc. Seminario Anual de Automática, Electrónica Industrial e Instrumentación (SAAEI, Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation)”. pp. “–”. “Vigo (Spain)”. ISBN: “84-688-3055-6”. bibtex

@inproceedings{ostua03-2,
	author = "E. Ostua and M.~J. Bellido and A. Barriga and P. Ruiz-de-Clavijo and J. Juan and A. Millan and D. Guerrero",
	title = "Diseño e implementación sobre FPGA de un microprocesador empotrable en SOC de Control",
	booktitle = "Proc. Seminario Anual de Automática, Electrónica Industrial e Instrumentación (SAAEI, Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation)",
	address = "Vigo (Spain)",
	month = "September",
	year = "2003",
	pages = "--", 
	isbn = "84-688-3055-6"
}

(“March” “2003”) “Internode: Internal node logic computational model”. In “Proc. 36th Annual Simulation Symposium (Advanced Simulation Technologies Conference, ASTC)”. pp. “241–248”. “Orlando, FL (United States of America)”. ISBN: “0-7695-1911-3”. bibtex

@inproceedings{millan03-2,
	author = "A. Millan and M.~J. Bellido and J. Juan and D. Guerrero and P. Ruiz-de-Clavijo and E. Ostua",
	title = "Internode: Internal node logic computational model",
	booktitle = "Proc. 36th Annual Simulation Symposium (Advanced Simulation Technologies Conference, ASTC)",
	address = "Orlando, FL (United States of America)",
	month = "March",
	year = "2003",
	pages = "241--248", 
	isbn = "0-7695-1911-3"
}

"2002" (6)

(“November” “2002”) “Two phase alternating latches clocking scheme for CMOS sequential circuits”. In “Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “159–162”. “Santander (Spain)”. bibtex

@inproceedings{guerrero02,
	author = "D. Guerrero and M.~J. Bellido and J. Juan and P. Paulino and A. Millan",
	title = "Two phase alternating latches clocking scheme for CMOS sequential circuits",
	booktitle = "Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Santander (Spain)",
	month = "November",
	year = "2002",
	pages = "159--162"
}

(“November” “2002”) “Integration of a characterization method for normal propagation delay into AUTODDM”. In “Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “93–97”. “Santander (Spain)”. bibtex

@inproceedings{millan02-2,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Integration of a characterization method for normal propagation delay into AUTODDM",
	booktitle = "Proc. 17th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Santander (Spain)",
	month = "November",
	year = "2002",
	pages = "93--97"
}

(“September” “2002”) “Measurement of the switching activity of CMOS digital circuits at the gate level”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “2451” pp. “353–362”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-44143-4”. doi bibtex

@inproceedings{baena02,
	author = "C. Baena and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and M. Valencia",
	title = "Measurement of the switching activity of CMOS digital circuits at the gate level",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "2451",
	month = "September",
	year = "2002",
	pages = "353--362",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-44143-4",
	doi = "10.1007/3-540-45716-X_35"
}

(“September” “2002”) “Characterization of normal propagation delay for Delay Degradation Model (DDM)“. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “2451” pp. “477–486”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-44143-4”. doi bibtex

@inproceedings{millan02-1,
	author = "A. Millan and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Characterization of normal propagation delay for Delay Degradation Model (DDM)",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "2451",
	month = "September",
	year = "2002",
	pages = "477--486",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-44143-4",
	doi = "10.1007/3-540-45716-X_48"
}

(“September” “2002”) “Efficient and fast current curve estimation of CMOS digital circuits at the logic level”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “2451” pp. “400–408”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-44143-4”. doi bibtex

@inproceedings{clavijo02,
	author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A. Millan and D. Guerrero",
	title = "Efficient and fast current curve estimation of CMOS digital circuits at the logic level",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "2451",
	month = "September",
	year = "2002",
	pages = "400--408",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-44143-4",
	doi = "10.1007/3-540-45716-X_40"
}

(“May” “2002”) “Design of a Microprocessor for SOC applications”. In “Proc. 4th European Workshop on Microelectronics Education (EWME)”. pp. “149–152”. “Vigo (Spain)”. ISBN: “84-267-1325-4”. bibtex

@inproceedings{estevez02,
	author = "M. Estevez and M.~J. Bellido and C.~J. Jimenez and J. Juan",
	title = "Design of a Microprocessor for SOC applications",
	booktitle = "Proc. 4th European Workshop on Microelectronics Education (EWME)",
	address = "Vigo (Spain)",
	month = "May",
	year = "2002",
	pages = "149--152", 
	isbn = "84-267-1325-4"
}

"2001" (7)

(“November” “2001”) “Simulation-driven switching activity evaluation of CMOS digital circuits”. In “Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “608–612”. “Porto (Portugal)”. bibtex

@inproceedings{baena01,
	author = "C. Baena and J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and M. Valencia",
	title = "Simulation-driven switching activity evaluation of CMOS digital circuits",
	booktitle = "Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Porto (Portugal)",
	month = "November",
	year = "2001",
	pages = "608--612"
}

(“November” “2001”) “ISS: Interactive Simulation System”. In “Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “410–413”. “Porto (Portugal)”. bibtex

@inproceedings{clavijo01-1,
	author = "P. Ruiz-de-Clavijo and M.~J. Bellido and J. Juan and C. Baena",
	title = "ISS: Interactive Simulation System",
	booktitle = "Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Porto (Portugal)",
	month = "November",
	year = "2001",
	pages = "410--413"
}

(“September” “2001”) “AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model”. In “Proc. International Conference on Electronics, Circuits and Systems (ICECS)”. pp. “1631–1634”. “Malta”. ISBN: “0-7803-7057-0”. bibtex

@inproceedings{juan01-2,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C. Baena and M. Valencia",
	title = "AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model",
	booktitle = "Proc. International Conference on Electronics, Circuits and Systems (ICECS)",
	address = "Malta",
	month = "September",
	year = "2001",
	pages = "1631--1634", 
	isbn = "0-7803-7057-0"
}

(“September” “2001”) “DDM characterization methodology and automation”. In “Proc. 11th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)”. pp. “5.2.1–5.2.10”. “Yverdon-Les-Bains (Switzerland)”. bibtex

@inproceedings{juan01-3,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C. Baena and M. Valencia",
	title = "DDM characterization methodology and automation",
	booktitle = "Proc. 11th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)",
	address = "Yverdon-Les-Bains (Switzerland)",
	month = "September",
	year = "2001",
	pages = "5.2.1--5.2.10"
}

(“June” “2001”) “Logic-timing simulation using the Degradation Delay Model”. In “Proc. International Workshop on Logic and Synthesis (IWLS)”. pp. “237–242”. “Granlibakken, CA (United States of America)”. bibtex

@inproceedings{juan01-1,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and C.~J. Jimenez and C. Baena and M. Valencia",
	title = "Logic-timing simulation using the Degradation Delay Model",
	booktitle = "Proc. International Workshop on Logic and Synthesis (IWLS)",
	address = "Granlibakken, CA (United States of America)",
	month = "June",
	year = "2001",
	pages = "237--242"
}

(“May” “2001”) “Gate-level simulation of CMOS circuits using the IDDM model”. In “Proc. IEEE International Symposium on Circuits and Systems (ISCAS)”. pp. “483–486”. “Darling Harbour, Sydney (Australia)”. ISBN: “0-7803-6687-5”. bibtex

@inproceedings{bellido01,
	author = "M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
	title = "Gate-level simulation of CMOS circuits using the IDDM model",
	booktitle = "Proc. IEEE International Symposium on Circuits and Systems (ISCAS)",
	address = "Darling Harbour, Sydney (Australia)",
	month = "May",
	year = "2001",
	pages = "483--486", 
	isbn = "0-7803-6687-5"
}

(“March” “2001”) “HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model”. In “Proc. Conference on Design, Automation and Test in Europe (DATE)”. pp. “467–471”. “Munich (Germany)”. ISBN: “0-7695-0993-2”. bibtex

@inproceedings{clavijo01-2,
	author = "P. Ruiz-de-Clavijo and J. Juan and M.~J. Bellido and A.~J. Acosta and M. Valencia",
	title = "HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model",
	booktitle = "Proc. Conference on Design, Automation and Test in Europe (DATE)",
	address = "Munich (Germany)",
	month = "March",
	year = "2001",
	pages = "467--471", 
	isbn = "0-7695-0993-2"
}

"2000" (4)

(“November” “2000”) “Gate-Level Modeling of the Delay Degradation Effect”. In “Proc. 15th Conference on Design of Circuits and Integrated Systems (DCIS)”. pp. “537–542”. “Montpellier - Le Corum (France)”. bibtex

@inproceedings{juan00-3,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
	title = "Gate-Level Modeling of the Delay Degradation Effect",
	booktitle = "Proc. 15th Conference on Design of Circuits and Integrated Systems (DCIS)",
	address = "Montpellier - Le Corum (France)",
	month = "November",
	year = "2000",
	pages = "537--542"
}

(“September” “2000”) “Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “1918” pp. “316–326”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-41068-3”. doi bibtex

@inproceedings{acosta00,
	author = "A.~J. Acosta and R. Jimenez and J. Juan and M.~J. Bellido and M. Valencia",
	title = "Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "1918",
	month = "September",
	year = "2000",
	pages = "316--326",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-41068-3",
	doi = "10.1007/3-540-45373-3_33"
}

(“September” “2000”) “Degradation delay model extension to CMOS gates”. In “Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation”. “Lecture Notes in Computer Science” “1918” pp. “149–158”. “Springer Berlin Heidelberg”. ISBN: “978-3-540-41068-3”. doi bibtex

@inproceedings{juan00-2,
	author = "J. Juan and M.~J. Bellido and P. Ruiz-de-Clavijo and A.~J. Acosta and M. Valencia",
	title = "Degradation delay model extension to CMOS gates",
	booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation",
	series = "Lecture Notes in Computer Science",
	volume = "1918",
	month = "September",
	year = "2000",
	pages = "149--158",
	publisher = "Springer Berlin Heidelberg",
	isbn = "978-3-540-41068-3",
	doi = "10.1007/3-540-45373-3_15"
}

(“May” “2000”) “Inertial and Degradation Delay Model for CMOS Logic Gates”. In “Proc. IEEE International Symposium on Circuits and Systems (ISCAS)”. pp. “459–462”. “Geneva (Switzerland)”. ISBN: “0-7803-5485-0”. bibtex

@inproceedings{juan00-1,
	author = "J. Juan and P. Ruiz-de-Clavijo and M.~J. Bellido and A.~J. Acosta and M. Valencia",
	title = "Inertial and Degradation Delay Model for CMOS Logic Gates",
	booktitle = "Proc. IEEE International Symposium on Circuits and Systems (ISCAS)",
	address = "Geneva (Switzerland)",
	month = "May",
	year = "2000",
	pages = "459--462", 
	isbn = "0-7803-5485-0"
}

PhD dissertations

All (6)

(“2016”) “Implementación sobre hardware reconfigurable de una arquitectura no determinista, paralela y distribuida de alto rendimiento, basada en modelos de computación con membranas”. “Universidad de Sevilla”. “Advisors: A. Millan and J. Viejo”.

Abstract bibtex

@PHDTHESIS{quiros16,
   author = "J. Quiros",
   title = "Implementación sobre hardware reconfigurable de una arquitectura no determinista, paralela y distribuida de alto rendimiento, basada en modelos de computación con membranas",
   school = "Universidad de Sevilla",
   note = "Advisors: A. Millan and J. Viejo",
   year = "2016",
   abstract = "En este documento se presenta el trabajo de tesis doctoral realizado dentro del Programa de Doctorado "Informática Industrial" del Departamento de Tecnología Electrónica de la Universidad de Sevilla. Recoge la investigación centrada en el desarrollo de una implementación en hardware reconfigurable, FPGA, de modelos de computación basados en membranas, también denominados sistemas P. Estos sistemas, de inspiración biológica, son de reciente creación, y tienen aplicaciones directas en procesos de simulación, especialmente de sistemas y procesos biológicos. Se engloban dentro de la computación natural, y se trata de modelos paralelos maximales orientados a máquinas. Este hecho supone un desafío en el desarrollo de implementaciones hardware, ya que es precisa la generación de un diseño diferente para cada problema, incluso para cada instancia. Como consecuencia directa, es necesario el desarrollo de una arquitectura hardware dedicada parametrizada, junto con un desarrollo software, que analice los sistemas de entrada y, en base a sus características, construya un diseño sintetizable dedicado para esa instancia concreta. Además, al ser la disciplina de reciente creación, existen distintos tipos de sistemas P, por lo que es preciso un análisis previo, seguido de una selección, con el propósito de implementar el mayor subconjunto posible de los mismos."
}

(“2012”) “Técnicas de Implementación de Circuitos Integrados Digitales CMOS de Alta Velocidad de Operación y Bajo Consumo de Potencia”. “Universidad de Sevilla”. “Advisors: M. J. Bellido and J. Juan”.

Abstract “Los sistemas digitales actuales se caracterizan por su alta velocidad de operación y su elevada miniaturización (podemos encontrar del orden de miles de millones de componentes en un solo circuito integrado). La evolución de la tecnología electrónica a lo largo de las últimas décadas ha permitido desarrollar los sistemas digitales y las comunicaciones de forma espectacular y, a medio plazo, no parece que vaya a ser sustituida por otra tecnología. El diseño de circuitos y sistemas digitales se enfrenta continuamente con nuevos retos a la hora de mejorar sus prestaciones, sobre todo a la hora de aumentar su velocidad de operación y reducir su consumo de energía. Esta tesis aborda estos dos problemas estudiando y proponiendo mejoras en los dispositivos digitales actuales de cara a aumentar su velocidad de operación y reducir su consumo. En concreto se centra en sistemas digitales construidos en tecnología MOS (Metal-Oxide-Semiconductor, Semiconductor-Óxido-Metal), que es la más ampliamente utilizada. Así mismo, se estudian los esquemas de sincronización empleados en los circuitos digitales y se plantean alternativas que permitan mejorar su rendimiento. En la primera parte de la tesis se constata que el usar puertas estáticas CMOS usando terminales body independientes (INBO) permite mejorar notablemente el consumo estático y dinámico así como la velocidad de las puertas lógicas CMOS estáticas. Además, las puertas INBO presentan un consumo estático y un retraso pin-a-pin más uniforme a lo largo de sus entradas, lo que es deseable de cara a la síntesis automatizada de circuitos lógicos. Las mejoras introducidas en la implementación INBO se obtienen a costa de una mayor área. Podría argumentarse que los transistores de las puertas de diseño convencional podrían redimensionarse hasta que ocupasen el área de sus homólogas INBO para aumentar su conductividad y velocidad pero esto es engañoso ya que al aumentar el tamaño de los transistores de una puerta se aumenta también su capacidad de entrada, de modo que las puertas que atacan dicha capacidad (es decir, aquellas cuya salida se ha conectado a las capacidades de entrada sobredimensionadas) aumentarían su consumo y reducirían su velocidad. Esto no ocurre al usar puertas INBO dado que su capacidad de entrada no aumenta respecto a sus homólogas COBO (aunque su tamaño sea mayor). Es más, dado que los terminales body de los transistores de las puertas INBO no están polarizados sus capacidades puerta-body se cargan a un menor voltaje, con lo que la velocidad de las puertas que generan las entradas de la puerta INBO mejora. A pesar de todo lo expuesto, la penalización de área introducida por las puertas INBO es muy severa, por lo que resultaría muy costoso que reemplazasen a las puertas tradicionales en todo el diseño. En lugar de eso, se propone usar las puertas INBO selectivamente en caminos críticos, nodos con alta actividad de conmutación o cuando se requieran puertas de gran número de entradas. Los algoritmos actuales de diseño incremental podrían aplicarse para hacer esta sustitución selectiva. Esto permitiría mejorar de forma significativa las prestaciones del circuito con un coste aceptable. Con respecto al estudio de los esquemas de sincronización, en la segunda parte de la tesis se proponen dos nuevos esquemas de sincronización basados en latches que operan de forma alternativa (PALACS) empleando dos o cuatro fases de reloj. Se ha establecido un procedimiento para obtener las formas de onda de máxima frecuencia de operación para un determinado clock skew tanto en estos esquemas como en el esquema másterslave. Asimismo, se verifica que, efectivamente, los esquemas PALACS propuestos son tolerantes al clock skew. Por otra parte, se realiza un análisis comparativo de la máxima frecuencia de operación para los esquemas propuestos y el esquema máster-slave. Los esquemas PALACS ofrecen una mayor velocidad de operación para prácticamente cualquier valor de skew, tendiendo, para valores altos del mismo, a una mejora del 100% respecto al máster-slave. Por último, se comprueba como, efectivamente, los esquemas PALACS suponen un ahorro muy significativo del consumo de energía, fundamentalmente porque reducen la potencia consumida en la red de distribución de reloj, aspecto cada vez más importante en las tecnologías actuales.” bibtex

@PHDTHESIS{guerrero12,
   author = "D. Guerrero",
   title = "Técnicas de Implementación de Circuitos Integrados Digitales CMOS de Alta Velocidad de Operación y Bajo Consumo de Potencia",
   school = "Universidad de Sevilla",
   note = "Advisors: M.~J. Bellido and J. Juan",
   year = "2012",
   abstract = "Los sistemas digitales actuales se caracterizan por su alta velocidad de operación y su elevada miniaturización (podemos encontrar del orden de miles de millones de componentes en un 
solo circuito integrado). La evolución de la tecnología electrónica a lo largo de las últimas décadas ha permitido desarrollar los sistemas digitales y las comunicaciones de forma espectacular y, a medio plazo, no parece que vaya a ser sustituida por otra tecnología.
El diseño de circuitos y sistemas digitales se enfrenta continuamente con nuevos retos a la hora de mejorar sus prestaciones, sobre todo a la hora de aumentar su velocidad de operación y reducir su consumo de energía. Esta tesis aborda estos dos problemas estudiando y proponiendo mejoras en los dispositivos digitales actuales de cara a aumentar su velocidad de operación y reducir su consumo. En concreto se centra en sistemas digitales construidos en tecnología MOS (Metal-Oxide-Semiconductor, Semiconductor-Óxido-Metal), que es la más ampliamente utilizada. Así mismo, se estudian los esquemas de sincronización empleados en los circuitos digitales y se plantean alternativas que permitan mejorar su rendimiento.
En la primera parte de la tesis se constata que el usar puertas estáticas CMOS usando terminales body
independientes (INBO) permite mejorar notablemente el consumo estático y dinámico así como la velocidad de las puertas lógicas CMOS estáticas. Además, las puertas INBO presentan un consumo estático y un retraso pin-a-pin más uniforme a lo largo de sus entradas, lo que es deseable de cara a la síntesis automatizada de circuitos lógicos.
Las mejoras introducidas en la implementación INBO se obtienen a costa de una mayor área. Podría argumentarse
que los transistores de las puertas de diseño convencional podrían redimensionarse hasta que ocupasen el área de sus homólogas INBO para aumentar su conductividad y velocidad pero esto es engañoso ya que al aumentar el
tamaño de los transistores de una puerta se aumenta también su capacidad de entrada, de modo que las puertas
que atacan dicha capacidad (es decir, aquellas cuya salida se ha conectado a las capacidades de entrada
sobredimensionadas) aumentarían su consumo y reducirían su velocidad. 
Esto no ocurre al usar puertas INBO dado que su capacidad de entrada no aumenta respecto a sus homólogas 
COBO (aunque su tamaño sea mayor).
Es más, dado que los terminales body de los transistores de las puertas INBO no están polarizados sus
capacidades puerta-body se cargan a un menor voltaje, con lo que la velocidad de las puertas que generan las
entradas de la puerta INBO mejora.
A pesar de todo lo expuesto, la penalización de área introducida por las puertas INBO es muy severa, por lo que resultaría muy costoso que reemplazasen a las puertas tradicionales en todo el diseño. En lugar de eso, se propone usar las puertas INBO selectivamente en caminos críticos, nodos con alta actividad de conmutación o cuando se requieran puertas de gran número de entradas. Los algoritmos actuales de diseño incremental podrían aplicarse para hacer esta sustitución selectiva. Esto permitiría mejorar de forma significativa las prestaciones del circuito con un coste aceptable.
Con respecto al estudio de los esquemas de sincronización, en la segunda parte de la tesis se proponen dos
nuevos esquemas de sincronización basados en latches que operan de forma alternativa (PALACS) empleando
dos o cuatro fases de reloj. Se ha establecido un procedimiento para obtener las formas de onda de máxima
frecuencia de operación para un determinado clock skew tanto en estos esquemas como en el esquema másterslave.
Asimismo, se verifica que, efectivamente, los esquemas PALACS propuestos son tolerantes al clock skew.
Por otra parte, se realiza un análisis comparativo de la máxima frecuencia de operación para los esquemas
propuestos y el esquema máster-slave. Los esquemas PALACS ofrecen una mayor velocidad de operación para
prácticamente cualquier valor de skew, tendiendo, para valores altos del mismo, a una mejora del 100% respecto al máster-slave.
Por último, se comprueba como, efectivamente, los esquemas PALACS suponen un ahorro muy significativo del
consumo de energía, fundamentalmente porque reducen la potencia consumida en la red de distribución de reloj,
aspecto cada vez más importante en las tecnologías actuales."
}

(“2011”) “Diseño e implementación sobre FPGA de sistemas digitales de bajo coste para la sincronización de equipos sobre redes de comunicación usando el protocolo SNTP”. “Universidad de Sevilla”. “Advisors: J. Juan and A. Millan”.

Abstract bibtex

@PHDTHESIS{viejo11,
   author = "J. Viejo",
   title = "Dise\~no e implementación sobre FPGA de sistemas digitales de bajo coste para la sincronización de equipos sobre redes de comunicación usando el protocolo SNTP",
   school = "Universidad de Sevilla",
   note = "Advisors: J. Juan and A. Millan",
   year = "2011",
   abstract = "En este trabajo se aborda el diseño e implementación sobre dispositivos programables FPGA de sistemas digitales dedicados a la sincronización de equipos sobre redes de comunicación empleando el protocolo estándar SNTP. Estos sistemas presentan una serie de características innovadoras respecto de las alternativas de sincronización existentes en la actualidad, ya que se trata de dispositivos autónomos, compactos, precisos y de bajo coste y consumo de potencia. Esto posibilita la integración de servicios de sincronización en sistemas empotrados, de forma que no sea necesario emplear ningún dispositivo externo que elimine las ventajas de este tipo de sistemas. Sin embargo, la implementación de estos servicios en hardware supone un reto ya que resulta necesario, por un lado, el desarrollo teórico de algoritmos de sincronización y de sistemas de control del reloj adecuados y, por otro, el desarrollo de aspectos prácticos, como por ejemplo, la implementación hardware de la pila de protocolos de comunicación o la recepción y transmisión de la información temporal."
}

(“2008”) “Técnicas de optimización para el modelado y la caracterización del comportamiento dinámico de circuitos digitales CMOS en tecnologías UDSM”. “Universidad de Sevilla”. “Advisors: M. J. Bellido and J. Juan”.

Abstract bibtex

@PHDTHESIS{millan08,
   author = " A. Millan",
   title = "Técnicas de optimización para el modelado y la caracterización del comportamiento dinámico de circuitos digitales CMOS en tecnologías UDSM",
   school = "Universidad de Sevilla",
   note = "Advisors: M.~J. Bellido and J. Juan",
   year = "2008",
   abstract = "En este documento se presentan dos trabajos originales orientados a la mejora de prestaciones de la simulación lógica temporal de circuitos digitales CMOS. En primer lugar, se presenta el algoritmo Internode. Se trata de un nuevo modelo para puertas lógicas, que permite contemplar el estado interno de éstas durante la simulación. Esto posibilita la inclusión de efectos asociados a dicho estado interno lo que, por su parte, aumenta de forma considerable la precisión de la simulación lógica temporal. En segundo lugar, se presenta el método Transample. Se trata de un nuevo método de caracterización basado en el empleo de señales muestreadas, que permite realizar los procesos de medida mediante curvas de entrada muy similares a las reales. Esto permite reducir sustancialmente el error cometido durante el propio proceso de caracterización lo que también mejora de manera importante la precisión de este tipo de simulaciones."
}

(“2007”) “Simulación lógica temporal de altas prestaciones y aplicación a la estimación del consumo de potencia y corriente en circuitos integrados CMOS-VLSI”. “Universidad de Sevilla”. “Advisors: M. J. Bellido and J. Juan”.

Abstract bibtex

@PHDTHESIS{ruiz07,
   author = "P. Ruiz-de-Clavijo",
   title = "Simulación lógica temporal de altas prestaciones y aplicación a la estimación del consumo de potencia y corriente en circuitos integrados CMOS-VLSI",
   school = "Universidad de Sevilla",
   note = "Advisors: M.~J. Bellido and J. Juan",
   year = "2007",
   abstract = "Se presenta un simulador lógico temporal, denominado HALOTIS que incluye modelos de muy alta prestación en cuanto a los resultados que se generan en la simulación lógica temporal de circuitos y sistemas digitales. Además, se ha elaborado un modelo de consumo de potencia que se ha incorporado al simulador consiguiendo resultados de gran precisión en cuanto a la medida del consumo de intensidad y potencia de los circuitos digitales desde la simulación lógica con las ventajas que supone respecto de la simulación eléctrica en cuanto a recursos tanto de CPU como otro tipo."
}

(“2000”) “Degradación del retraso de propagación en puertas lógicas CMOS VLSI”. “Universidad de Sevilla”. “Advisors: M. J. Bellido and M. Valencia”.

Abstract “ Una de las tareas más importantes en el diseño de Circuitos Integrados (C.I.) digitales es la verificación de los diseños previa a la fabricación. La complejidad de los circuitos actuales hace necesario el empleo de ordenadores y de programas informáticos específicos para la realización de estas tareas. La herramienta principal para la verificación de C.I. digitales de altas prestaciones es el simulador temporal. En la actualidad se emplean dos tipos principales de simuladores: los de nivel eléctrico, que resultan muy precisos pero limitados en velocidad y tamaño máximo de circuito simulable; y los de nivel lógico, que son rápidos y pueden simular circuitos muy grandes, pero con una precisión relativamente baja. El aumento de la precisión de los simuladores lógico-temporales es la clave para la simulación de C.I. digitales de alta escala de integración (VLSI) y pasa por el desarrollo de modelos de retraso de alta precisión para estos simuladores. El objetivo de esta Tesis es desarrollar un modelo de retraso de gran precisión para la simulación de C.I. digitales fabricados en la tecnología más difundida (CMOS). El modelo desarrollado (DDM) contempla los efectos estudiados por otros autores e introduce el llamado “efecto de degradación del retraso”. El modelado de este efecto permite la simulación de circuitos que operan a altas frecuencias y el correcto tratamiento de pulsos pequeños o “glitches” y de las colisiones de señal en circuitos lógicos, ampliando de forma considerable el rango de aplicación de la simulación lógica-temporal. En primer lugar, la Tesis introduce el campo de la Verificación Temporal de C.I. Digitales y realiza un análisis de los modelos más relevantes presentados en los últimos diez años. A continuación se estidia la evolución de los modelos para el efecto de degradación y se proporciona un nuevo modelo para su comportamiento. Este modelo es desarrollado en detalle tanto para la celda básica (inversor CMOS) como para puertas lógicas más complejas, suministrando, así mismo, una descripción detallada del proceso de caracterización de los parámetros del modelo. Finalmante, se presenta un conjunto significativo de ejemplos de simulación comparando los resultados del DDM con los de simuladores eléctricos de alta precisión y con modelos lógicos que no contemplan el efecto de degradación. En todos los casos, los resultados del DDM muestran una precisión similar a los de la simulación eléctrica, mejorando muy significativamente los resultados de los modelos convencionales, mientras que conserva todas las ventajas de la simulación lógica-temporal.” bibtex

@PHDTHESIS{juan00,
   author = "J. Juan",
   title = "Degradación del retraso de propagación en puertas lógicas CMOS VLSI",
   school = "Universidad de Sevilla",
   note = "Advisors: M.~J. Bellido and M. Valencia",
   year = "2000",
   abstract = " Una de las tareas más importantes en el diseño de Circuitos Integrados (C.I.) digitales es la verificación de los diseños previa a la fabricación. La complejidad de los circuitos actuales hace necesario el empleo de ordenadores y de programas informáticos específicos para la realización de estas tareas. La herramienta principal para la verificación de C.I. digitales de altas prestaciones es el simulador temporal. En la actualidad se emplean dos tipos principales de simuladores: los de nivel eléctrico, que resultan muy precisos pero limitados en velocidad y tamaño máximo de circuito simulable; y los de nivel lógico, que son rápidos y pueden simular circuitos muy grandes, pero con una precisión relativamente baja. El aumento de la precisión de los simuladores lógico-temporales es la clave para la simulación de C.I. digitales de alta escala de integración (VLSI) y pasa por el desarrollo de modelos de retraso de alta precisión para estos simuladores. El objetivo de esta Tesis es desarrollar un modelo de retraso de gran precisión para la simulación de C.I. digitales fabricados en la tecnología más difundida (CMOS). El modelo desarrollado (DDM) contempla los efectos estudiados por otros autores e introduce el llamado "efecto de degradación del retraso". El modelado de este efecto permite la simulación de circuitos que operan a altas frecuencias y el correcto tratamiento de pulsos pequeños o "glitches" y de las colisiones de señal en circuitos lógicos, ampliando de forma considerable el rango de aplicación de la simulación lógica-temporal. En primer lugar, la Tesis introduce el campo de la Verificación Temporal de C.I. Digitales y realiza un análisis de los modelos más relevantes presentados en los últimos diez años. A continuación se estidia la evolución de los modelos para el efecto de degradación y se proporciona un nuevo modelo para su comportamiento. Este modelo es desarrollado en detalle tanto para la celda básica (inversor CMOS) como para puertas lógicas más complejas, suministrando, así mismo, una descripción detallada del proceso de caracterización de los parámetros del modelo. Finalmante, se presenta un conjunto significativo de ejemplos de simulación comparando los resultados del DDM con los de simuladores eléctricos de alta precisión y con modelos lógicos que no contemplan el efecto de degradación. En todos los casos, los resultados del DDM muestran una precisión similar a los de la simulación eléctrica, mejorando muy significativamente los resultados de los modelos convencionales, mientras que conserva todas las ventajas de la simulación lógica-temporal."
}

Teaching papers

"2022" (1)

(“June” “2022”) “Entorno de virtualización para la realización y evaluación de prácticas de laboratorio TIC”. In “Proc. 15th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)”. pp. “628–633”. “Teruel (Spain)”. ISBN: “978-84-09-42360-6”. bibtex

@inproceedings{viejo22,
	author = "J. Viejo-Cortes and P. Ruiz-de-Clavijo-Vazquez and E. Ostúa-Arangüena and J. Juan-Chico and G. Cano-Quiveu",
	title = "Entorno de virtualización para la realización y evaluación de prácticas de laboratorio TIC",
	booktitle = "Proc. 15th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)",
	address = "Teruel (Spain)",
	month = "June",
	year = "2022",
	pages = "628--633",
        isbn = "978-84-09-42360-6"
}

"2020" (1)

(“July” “2020”) “Experiencia en la adaptación de una asignatura de máster para su impartición completa a distancia”. In “Proc. 14th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)”. pp. “371–377”. “Porto (Portugal)”. ISBN: “978-989-54758-3-4”. bibtex

@inproceedings{viejo20,
	author = "J. Viejo-Cortes and A. Carrasco-Muñoz and J. Juan-Chico and P. Ruiz-de-Clavijo-Vazquez and G. Cano-Quiveu",
	title = "Experiencia en la adaptación de una asignatura de máster para su impartición completa a distancia",
	booktitle = "Proc. 14th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)",
	address = "Porto (Portugal)",
	month = "July",
	year = "2020",
	pages = "371--377",
        isbn = "978-989-54758-3-4"
}

"2016" (1)

(“June” “2016”) “Metodología PBL en modo colaborativo aplicada al diseño de un SoC”. In “Proc. 12th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)”. pp. “203–210”. “Sevilla (Spain)”. ISBN: “978-84-608-9298-4”. bibtex

@inproceedings{ruizdeclavijo16,
	author = "P. Ruiz-de-Clavijo and J. Juan and J. Viejo and M.~J. Bellido and E. Ostua and D. Guerrero",
	title = "Metodología PBL en modo colaborativo aplicada al diseño de un SoC",
	booktitle = "Proc. 12th Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE)",
	address = "Sevilla (Spain)",
	month = "June",
	year = "2016",
	pages = "203--210",
        isbn = "978-84-608-9298-4"
}

"2014" (1)

(“June” “2014”) “Application of virtualization technology to the study of quality of service techniques”. In “Technologies Applied to Electronics Teaching (TAEE) 2014 XI”. pp. “1–6”. “Bilbao (Spain)”. ISBN: “978-1-4799-6002-6”. doi bibtex

@inproceedings{quiros14,
	author = "J. Quiros and P. Ruiz-de-Clavijo and A. Carrasco and J. Viejo and A. Millan",
	title = "Application of virtualization technology to the study of quality of service techniques",
	booktitle = "Technologies Applied to Electronics Teaching (TAEE) 2014 XI",
	address = "Bilbao (Spain)",
	month = "June",
	year = "2014",
	pages = "1--6",
        isbn = "978-1-4799-6002-6",
        doi = {10.1109/TAEE.2014.6900179}
}

"2012" (2)

(“June” “2012”) “Methodology updating experience in basic digital electronics teaching”. In “Proc. 10th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “52–57”. “Vigo (Spain)”. ISBN: “978-84-8158-570-4”. doi bibtex

@inproceedings{juan12,
	author = "J. Juan and E. Ostua and D. Guerrero",
	title = "Methodology updating experience in basic digital electronics teaching",
	booktitle = "Proc. 10th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Vigo (Spain)",
	month = "June",
	year = "2012",
	pages = "52--57", 
        doi = {10.1109/TAEE.2012.6235407},
	isbn = "978-84-8158-570-4"
}

(“June” “2012”) “Implementation of a hardware and software framework for a simple academic processor”. In “Proc. 10th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “58–63”. “Vigo (Spain)”. ISBN: “978-84-8158-570-4”. doi bibtex

@inproceedings{ruiz12,
	author = "J. Ruiz and D. Guerrero and I. Gomez and J. Viejo",
	title = "Implementation of a hardware and software framework for a simple academic processor",
	booktitle = "Proc. 10th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Vigo (Spain)",
	month = "June",
	year = "2012",
	pages = "58--63", 
        doi = {10.1109/TAEE.2012.6235405},
	isbn = "978-84-8158-570-4"
}

"2011" (2)

(“2011”) “Evaluación multiagente en la formación de profesores noveles”. In “Programa de equipos docentes de la Universidad de Sevilla Cursos 2004-2005 a 2007-2008”. pp. “263–276”. “Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla”. ISBN: “978-84-86849-37-3”. bibtex

@inbook{benjumea11,
	author = "J. Benjumea and A. Estrada and E. Ostua and O. Rivera and J. Ropero and F. Sivianes and M. Valencia",
	title = "Evaluación multiagente en la formación de profesores noveles",
	editor = "J.~M. de Mesa, R.~J. Casta\~neda, M. Sanchez, C. Mayor",
	booktitle = "Programa de equipos docentes de la Universidad de Sevilla Cursos 2004-2005 a 2007-2008",
	publisher = "Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla",
	year = "2011",
	chapter = "Curso 2006--2007",
	pages = "263--276",
	isbn = "978-84-86849-37-3"
}

(“2011”) “Experiencias del Equipo Docente de Iniciación en el Departamento de Tecnología Electrónica”. In “Programa de equipos docentes de la Universidad de Sevilla Cursos 2004-2005 a 2007-2008”. pp. “395–405”. “Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla”. ISBN: “978-84-86849-37-3”. bibtex

@inbook{miro11,
	author = "G. Miro and J. Viejo and M. Valencia",
	title = "Experiencias del Equipo Docente de Iniciación en el Departamento de Tecnología Electrónica",
	editor = "J.~M. de Mesa, R.~J. Casta\~neda, M. Sanchez, C. Mayor",
	booktitle = "Programa de equipos docentes de la Universidad de Sevilla Cursos 2004-2005 a 2007-2008",
	publisher = "Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla",
	year = "2011",
	chapter = "Curso 2007--2008",
	pages = "395--405",
	isbn = "978-84-86849-37-3"
}

"2009" (1)

(“2009”) “Aplicación de técnicas de evaluación continua en grupos numerosos de alumnos”. In “Experiencia de Innovación Universitaria (I)”. pp. “350–365”. “Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla”. ISBN: “978-84-86849-70-2”. bibtex

@inbook{baena09,
	author = "M.~C. Baena and M.~J. Bellido and A. Estrada and J. Juan and S. Martin and A.~J. Molina and E. Ostua and M.~P. Parra and O. Rivera and M.~C. Romero and J. Ropero and P. Ruiz de Clavijo and G. Sanchez and M. Valencia and J.~M. Gomez",
	title = "Aplicación de técnicas de evaluación continua en grupos numerosos de alumnos",
	booktitle = "Experiencia de Innovación Universitaria (I)",
	publisher = "Instituto de Ciencias de la Educación, Vicerrectorado de Docencia, Universidad de Sevilla",
	year = "2009",
	chapter = "Curso 2006--2007",
        vol = "1",
	pages = "350--365",
	isbn = "978-84-86849-70-2"
}

"2008" (6)

(“July” “2008”) “Desarrollo de una interfaz RS-232 para el manejo de un coche de radiocontrol desde el PC”. In “Proc. 8th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “119”. “Zaragoza (Spain)”. ISBN: “978-84-7733-628-0”. bibtex

@inproceedings{munoz08-1,
	author = "A. Mu\~noz and A. Millan and P. Ruiz-de-Clavijo and J. Viejo and E. Ostua and D. Guerrero",
	title = "Desarrollo de una interfaz RS-232 para el manejo de un coche de radiocontrol desde el PC",
	booktitle = "Proc. 8th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Zaragoza (Spain)",
	month = "July",
	year = "2008",
	pages = "119", 
	isbn = "978-84-7733-628-0"
}

(“July” “2008”) “Ampliación de periféricos para aplicaciones embebidas basadas en hardware y software libre”. In “Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “978-84-00-08680-0”. bibtex

@inproceedings{munoz08-2,
	author = "A. Mu\~noz and E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and J.~I. Villar and J. Quiros",
	title = "Ampliación de periféricos para aplicaciones embebidas basadas en hardware y software libre",
	booktitle = "Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2008",
	pages = "--", 
	isbn = "978-84-00-08680-0"
}

(“July” “2008”) “La primera experiencia en el diseño de sistemas digitales sobre FPGAs”. In “Proc. 8th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “161”. “Zaragoza (Spain)”. ISBN: “978-84-7733-628-0”. bibtex

@inproceedings{viejo08-1,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and D. Guerrero and A. Mu\~noz",
	title = "La primera experiencia en el diseño de sistemas digitales sobre FPGAs",
	booktitle = "Proc. 8th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Zaragoza (Spain)",
	month = "July",
	year = "2008",
	pages = "161", 
	isbn = "978-84-7733-628-0"
}

(“July” “2008”) “Aplicación de Picoblaze al diseño de sistemas de control industrial”. In “Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “978-84-00-08680-0”. bibtex

@inproceedings{viejo08-2,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Mu\~noz and A. Millan",
	title = "Aplicación de Picoblaze al diseño de sistemas de control industrial",
	booktitle = "Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2008",
	pages = "--", 
	isbn = "978-84-00-08680-0"
}

(“July” “2008”) “Metodología de diseño SOC con OpenRISC sobre FPGA”. In “Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “978-84-00-08680-0”. bibtex

@inproceedings{villar08,
	author = "J.~I. Villar and M.~J. Bellido and E. Ostua and D. Guerrero and J. Juan and A. Mu\~noz",
	title = "Metodología de diseño SOC con OpenRISC sobre FPGA",
	booktitle = "Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2008",
	pages = "--", 
	isbn = "978-84-00-08680-0"
}

(“2008”) “Tecnología de Computadores: Asignaturas en Red. Plan de Renovación de Metodologías Docentes”. “Universidad de Sevilla”. ISBN: “978-84-691-1460-5”. bibtex

@inbook{yufera08,
	author = "A. Yufera and J. Barbancho and E. Ostua and A. Estrada",
	title = "Tecnología de Computadores: Asignaturas en Red. Plan de Renovación de Metodologías Docentes",
	publisher = "Universidad de Sevilla",
	year = "2008",
	isbn = "978-84-691-1460-5"
}

"2006" (3)

(“July” “2006”) “Desarrollo en VHDL de un filtro digital genérico basado en estructuras canónicas”. In “Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “285–286”. “Madrid (Spain)”. ISBN: “84-689-9590-8”. bibtex

@inproceedings{alvarez06,
	author = "A. Alvarez and A. Millan and M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and J. Viejo",
	title = "Desarrollo en VHDL de un filtro digital genérico basado en estructuras canónicas",
	booktitle = "Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Madrid (Spain)",
	month = "July",
	year = "2006",
	pages = "285--286", 
	isbn = "84-689-9590-8"
}

(“July” “2006”) “Introducción de dispositivos programables en prácticas de laboratorio”. In “Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “135–136”. “Madrid (Spain)”. ISBN: “84-689-9590-8”. bibtex

@inproceedings{jimenez06,
	author = "C.~J. Jimenez and C. Baena and E. Ostua and M. Valencia",
	title = "Introducción de dispositivos programables en prácticas de laboratorio",
	booktitle = "Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Madrid (Spain)",
	month = "July",
	year = "2006",
	pages = "135--136", 
	isbn = "84-689-9590-8"
}

(“July” “2006”) “Diseño e implementación de SOPC basados en el microprocesador PicoBlaze”. In “Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “319–320”. “Madrid (Spain)”. ISBN: “84-689-9590-8”. bibtex

@inproceedings{viejo06,
	author = "J. Viejo and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero",
	title = "Diseño e implementación de SOPC basados en el microprocesador PicoBlaze",
	booktitle = "Proc. 7th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Madrid (Spain)",
	month = "July",
	year = "2006",
	pages = "319--320", 
	isbn = "84-689-9590-8"
}

"2005" (1)

(“2005”) “La formación del profesorado universitario”. In “Programa de equipos docentes de la Universidad de Sevilla”. pp. “75–84”. “Instituto de Ciencias de la Educación, Vicerrectorado de Calidad y Nuevas Tecnologías, Universidad de Sevilla”. ISBN: “978-84-86849-37-3”. bibtex

@inbook{barbancho05,
	author = "J. Barbancho and D. Guerrrero and C.~J. Jimenez and M. Valencia",
	title = "La formación del profesorado universitario",
	booktitle = "Programa de equipos docentes de la Universidad de Sevilla",
	publisher = "Instituto de Ciencias de la Educación, Vicerrectorado de Calidad y Nuevas Tecnologías, Universidad de Sevilla",
	year = "2005",
	chapter = "Curso 2003--2004",
	pages = "75--84",
	isbn = "978-84-86849-37-3"
}

"2004" (6)

(“July” “2004”) “Diseño del microcontrolador 8051 con modulo ensamblador-generador de ROM en lenguaje VHDL”. In “Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “–”. “Valencia (Spain)”. ISBN: “84-688-7339-X”. bibtex

@inproceedings{franco04-1,
	author = "E. Franco and F. Montero and E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Millan and D. Guerrero and J. Juan",
	title = "Diseño del microcontrolador 8051 con modulo ensamblador-generador de ROM en lenguaje VHDL",
	booktitle = "Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Valencia (Spain)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-688-7339-X"
}

(“July” “2004”) “Microcontrolador 8051: compilador de ROM y diseño del micro en VHDL”. In “Proc. 3rd International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “84-8138-607-3”. bibtex

@inproceedings{franco04-2,
	author = "E. Franco and F. Montero and E. Ostua and M.~J. Bellido and P. Ruiz-de-Clavijo and A. Millan and D. Guerrero and J. Juan",
	title = "Microcontrolador 8051: compilador de ROM y diseño del micro en VHDL",
	booktitle = "Proc. 3rd International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-8138-607-3"
}

(“July” “2004”) “Análisis del comportamiento de la videoconsola Atari 2600 como sistema digital real basado en microprocesador en el laboratorio de Electronica”. In “Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “–”. “Valencia (Spain)”. ISBN: “84-688-7339-X”. bibtex

@inproceedings{guerrero04,
	author = "D. Guerrero and E. Ostua and M.~J. Bellido and J. Juan and A. Millan and P. Ruiz-de-Clavijo and J.~I. Villar",
	title = "Análisis del comportamiento de la videoconsola Atari 2600 como sistema digital real basado en microprocesador en el laboratorio de Electronica",
	booktitle = "Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Valencia (Spain)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-688-7339-X"
}

(“July” “2004”) “ADKI: un sistema web de adquisicion de datos bajo Linux”. In “Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “–”. “Valencia (Spain)”. ISBN: “84-688-7339-X”. bibtex

@inproceedings{jurado04-1,
	author = "P. Jurado and J. Juan and P. Ruiz-de-Clavijo and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua",
	title = "ADKI: un sistema web de adquisicion de datos bajo Linux",
	booktitle = "Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Valencia (Spain)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-688-7339-X"
}

(“July” “2004”) “Un sistema web para la adquisición de datos y control basado en GNU/Linux”. In “Proc. 3rd International Conference on Telecommunications, Electronics and Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “84-8138-607-3”. bibtex

@inproceedings{jurado04-2,
	author = "P. Jurado and J. Juan and P. Ruiz-de-Clavijo and M.~J. Bellido and A. Millan and D. Guerrero and E. Ostua",
	title = "Un sistema web para la adquisición de datos y control basado en GNU/Linux",
	booktitle = "Proc. 3rd International Conference on Telecommunications, Electronics and Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-8138-607-3"
}

(“July” “2004”) “Seguridad en Internet: Web Spoofing”. In “Proc. 6th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)”. pp. “–”. “Valencia (Spain)”. ISBN: “84-688-7339-X”. bibtex

@inproceedings{nunez04,
	author = "J.~L. Nuñez and A. Millan and P. Ruiz-de-Clavijo and D. Guerrero and E. Ostua and M.~J. Bellido and J. Juan",
	title = "Seguridad en Internet: Web Spoofing",
	booktitle = "Proc. 6th Congreso de Tecnologias Aplicadas a la Enseñanza de la Electronica (TAEE)",
	address = "Valencia (Spain)",
	month = "July",
	year = "2004",
	pages = "--", 
	isbn = "84-688-7339-X"
}

"2003" (1)

(“2003”) “Desarrollo de una aplicación del área de producción animal”. In “Innovaciones Docentes en la Universidad de Sevilla”. pp. “213–218”. “Instituto de Ciencias de la Educación, Vicerrectorado de Calidad y Nuevas Tecnologías, Universidad de Sevilla”. ISBN: “84-86849-29-2”. bibtex

@inbook{fernandez03,
	author = "V.~M. Fernandez and F.~P. Caravaca and J.~M. Castel and M. Delgado and M.~J. Alcalde and P. Gonzalez and Y. Mena and J. Barros and P. Ruiz-de-Clavijo and A. Millan",
	title = "Desarrollo de una aplicación del área de producción animal",
	booktitle = "Innovaciones Docentes en la Universidad de Sevilla",
	publisher = "Instituto de Ciencias de la Educación, Vicerrectorado de Calidad y Nuevas Tecnologías, Universidad de Sevilla",
	year = "2003",
	chapter = "Curso 2001--2002",
	pages = "213--218",
	isbn = "84-86849-29-2"
}

"2002" (2)

(“July” “2002”) “Design of a microprocessor for SOC applications”. In “Proc. 2nd Conferencia Internacional sobre Telecomunicación, Electrónica y Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “84-8138-506-9”. bibtex

@inproceedings{estevez02,
	author = "M. Estevez and M.~J. Bellido and C.~J. Jimenez and J. Juan",
	title = "Design of a microprocessor for SOC applications",
	booktitle = "Proc. 2nd Conferencia Internacional sobre Telecomunicación, Electrónica y Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2002",
	pages = "--", 
	isbn = "84-8138-506-9"
}

(“February” “2002”) “Sistema de control de grupos de prácticas: aplicación al ámbito docente del Departamento de Tecnología Electrónica de la Universidad de Sevilla”. In “Proc. 5th Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “503–506”. “Las Palmas de Gran Canaria (Spain)”. bibtex

@inproceedings{castro02,
	author = "J. Castro and A. Millan and P. Ruiz-de-Clavijo",
	title = "Sistema de control de grupos de prácticas: aplicación al ámbito docente del Departamento de Tecnología Electrónica de la Universidad de Sevilla",
	booktitle = "Proc. 5th Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Las Palmas de Gran Canaria (Spain)",
	month = "February",
	year = "2002",
	pages = "503--506"}

"2000" (2)

(“September” “2000”) “Concepción de un microprocesador: de la especificación a la realización”. In “Proc. 4th Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)”. pp. “565–568”. “Barcelona (Spain)”. ISBN: “84-600-9596-7”. bibtex

@inproceedings{bellido00-2,
	author = "M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A.~J. Acosta",
	title = "Concepción de un microprocesador: de la especificación a la realización",
	booktitle = "Proc. 4th Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE)",
	address = "Barcelona (Spain)",
	month = "September",
	year = "2000",
	pages = "565--568", 
	isbn = "84-600-9596-7"
}

(“July” “2000”) “Aplicación de ALLIANCE al diseño de Circuitos Digitales VLSI”. In “Proc. 1st Conferencia Internacional sobre Telecomunicación, Electrónica y Control (TELEC)”. pp. “–”. “Santiago de Cuba (Cuba)”. ISBN: “84-8138-393-7”. bibtex

@inproceedings{bellido00-1,
	author = "M.~J. Bellido and J. Juan and P. Ruiz-de-Clavijo and A. Barriga",
	title = "Aplicación de ALLIANCE al diseño de Circuitos Digitales VLSI",
	booktitle = "Proc. 1st Conferencia Internacional sobre Telecomunicación, Electrónica y Control (TELEC)",
	address = "Santiago de Cuba (Cuba)",
	month = "July",
	year = "2000",
	pages = "--", 
	isbn = "84-8138-393-7"
}

"1997" (1)

(“1997”) “Problemas de Circuitos y Sistemas Digitales”. “McGraw-Hill Interamericana, Madrid (Spain)”. ISBN: “84-481-0966-X”. bibtex

@book{baena97,
	author = "C. Baena and M.~J. Bellido and A. Molina and M.~P. Parra and M. Valencia",
	title = "Problemas de Circuitos y Sistemas Digitales",
	publisher = "McGraw-Hill Interamericana, Madrid (Spain)",
	year = "1997",
	isbn = "84-481-0966-X"
}

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