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HIPERSYS Project: HIPERSYS: HIgh PERformance embedded SYStems optimization



  • Type: Plan Nacional, 2011
  • Reference: TEC2011-27936
  • Start date: 01-01-2012
  • End date: 31-12-2014
  • Executing institution: Universidad de Sevilla
  • Funding institution: Ministerio de Ciencia e Innovación
  • Funds: 94100 Euros
  • Responsible: Dr. Jorge Juan Chico
  • Team: Manuel J. Bellido Díaz, Dr. Alejandro Millán Calderón, Dr. Paulino Ruiz de Clavijo Vázquez, David Guerrero Martos, Alejandro Muñoz Rivera, Enrique Ostúa Arangüena, Dr. Julián Viejo Cortés, José Ignacio Villar de Ossorno, Juan Quirós Carmona.


The general objective of the project is the development of fundamental knowledge and technology to optimize the performance of embedded systems by applying digital design techniques to problems where traditional software solutions are not adequate for different reasons: high cost, high complexity, low performance, high power consumption, etc. This project represents the natural evolution of the line of high performance digital system design and verification that our group has been working on for the past decade with the support from the Plan Nacional de Investigación. This proposal focuses in four main topics which are the current areas of interest of the group. These are:

  • Network synchronization protocols: development of the knowledge and technology to implement high accuracy and cost-effective network synchronization facilities in embedded systems. As a result, it should be possible to offer hardware support to all the main tasks involved in a network synchronization system based on the NTP or PTP standards: protocol, local clock control, clock disciplining, time stamping, etc.
  • Biocomputation: explore methods and techniques to implement efficient P-systems in reconfigurable hardware in order to overcome the limitations of simulating these systems in software. This area focuses on two variants of P systems: the transitive variant, as the originally proposed model by the creator of the discipline, Gheorghe Pãun, and the probabilistic variant, which makes use of probabilistic models that capture the non-deterministic behaviour.
  • Signal processing: integration of emerging high quality video standards in embedded systems. In particular, this area is dedicated to evaluate hardware solutions to implement the VP8 video codec, released by Google on 2010 through the WebM project, in embedded systems.
  • Design automation of System on Chip (SoC) embedded systems: exploration and testing high level methodologies to optimize the design of embedded systems.

Benefits and expected results

This project foresees the production of both scientific and technological benefits. At the scientific level, new methods, algorithms and system architectures are going to be developed in order to implement accurate synchronization solutions, bio-inspired computation systems and emerging video codecs in hardware. Because current solutions heavily relay on software in all these areas, most current algorithms and methods are not directly portable to hardware or they are simply inadequate. Because this project aim at producing very accurate yet very compact and cost-effective solutions that are suitable for embedded systems, this fundamental research in new methods, algorithms and architectures specially focused on full hardware implementations is both a necessity and an important scientific contribution itself.

The diffusion plan for scientific results is implemented by contributing communications to international conferences and journals. As depicted in the working plan and chronogram, this is an specific task that will be worked on twice a year (depending on conference calendar) in order to formalise and get feedback from the scientific community of our partial results. During the last year of the project, special effort will be devoted to journal papers.

This project also aim at obtaining true technology that can be used in industrial and consumer applications. The scientific research in this project can be used to implement a set of hardware building blocks that can be combine to provide synchronization functionality and/or advanced video coding/decoding facilities to any embedded system. These blocks can then be packaged as IP-cores (Intellectual Property cores) with well documented interfaces in order to maximise the opportunities to transfer the technology generated in the project. By the diffusion of these IP cores and by patenting their inner technology, we plan to expand the exploitation the project's results much beyond its finishing dates. On the other hand, the implementation of bio-inspired P Systems in hardware is a fundamental contribution to the field of membrane computing.

The technology transfer of the expected results are of an special interest in the industrial world as we had the opportunity to check in PROFIT projects PTC and SEPIC commanded by Telvent Energía company (see section 6.2) in which our group has been involved recently. Although this project focuses on fundamental research needed to produce new technology, we are confident that the results of this project will have an application in the industry in the short term and has a high potential to be a great benefit to the local and national industry.

en/projects/hipersys.txt · Last modified: 2018/01/12 13:09 by julian

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