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Dr. Jorge Juan received the Bsc. degree (1994) and the PhD. degree in Physics (2000) from the University of Seville, Spain. He is currently Associate Professor in the Electronics Technology Department at the same University where he is leadening the Digital Research and Development Group based at the Computer Engineering School. He has also been with the Institute of Microelectronics of Seville, part of the National Center of Microelectronics in Spain (CNM-CSIC), from 1995 to 2007. Dr. Juan has done research in the areas of metastability, delay modelling, timing and power simulation and digital embedded systems, where he has authored 2 complete books, one book chapter, numerous research papers in indexed journals and more than 40 conference papers. He has been guest editor for Springer-Verlag's Lecture Notes in Computer Science and the IEE Proceedings on Computers and Digital Techniques. He is member of the steering and program committees of the IEEE Workshop on Power and Timing Modelling (PATMOS) since 2002. He has also been scientific consultant for the University of Siena, the Spanish National Commission for Scientific Research Activity, several international journals like IEEE Trans. on Computers, Elsevier's Integration VLSI Journal; and international conferences like ISCAS and DATE. He has also participated in a number European and national research projects founded by the Spanish Government.