Journals
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J. Viejo, J. I. Villar, J. Juan, A. Millan, E. Ostua, J. Quiros
Long-term on-chip verification of systems with logical events scattered in time, Microprocessors and Microsystems 36 (5) pp. 402–408, Elsevier. United Kingdom. ISSN: 0141-9331 [Full article (PDF)]
Conference Proceedings
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D. Guerrero, E. Ostua, M. J. Bellido, J. Juan, A. Millan, P. Ruiz-de-Clavijo, J. I. Villar,
Análisis del comportamiento de la videoconsola Atari 2600 como sistema digital real basado en microprocesador en el laboratorio de Electronica, Proc. 6th Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE), Valencia, Spain, July 2004 [Full Paper (PDF)]
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J. I. Villar, M. J. Bellido, E. Ostua, D. Guerrero, J. Juan, A. Muñoz,
Metodología de diseño SOC con OpenRISC sobre FPGA, Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC), Santiago de Cuba, Cuba, July 2008 [Full Paper (PDF)]
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A. Muñoz, E. Ostua, M. J. Bellido, P. Ruiz-de-Clavijo, J. I. Villar, J. Quiros,
Ampliación de periféricos para aplicaciones embebidas basadas en hardware y software libre, Proc. 5th International Conference on Telecommunications, Electronics and Control (TELEC), Santiago de Cuba, Cuba, July 2008 [Full Paper (PDF)]
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J. I. Villar, M. J. Bellido, E. Ostua, D. Guerrero, J. Juan, A. Muñoz,
Metodología de Diseño de SoC basada en OpenRisc sobre FPGA con Cores y Herramientas Libres, Proc. 8th Conference on Reconfigurable Computing and Applications (JCRA), Madrid, Spain, September 2008 [Full Paper (PDF)]
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J. Viejo, J. Juan, E. Ostua, M. J. Bellido, A. Millan, A. Muñoz, J. I. Villar,
Accurate and compact implementation of a hardware SNTP Client, Proc. 15th Iberchip Workshop (IWS), Buenos Aires, Argentine, March 2009 [Full Paper (PDF)]
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J. I. Villar, Advisors: J. Juan, M. J. Bellido,
Efficient techniques and methodologies for embedded system design using free hardware and open standards, Proc. 19th International Conference on Field-Programmable Logic and Applications (FPL) Prague, Czech Republic, August 2009. (Thesis project) [Full Paper (PDF)]
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J. I. Villar, J. Juan, M. J. Bellido, P. Ruiz-deClavijo, D.Guerrero, A. Muñoz,
Usando Python como HDL: Estudio comparativo de resultados basado en el desarrollo de un periférico real, Proc. 9th Conference on Reconfigurable Computing and Applications (JCRA), Madrid Spain, September 2009 [Full Paper (PDF)]
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J. Viejo, J. Juan, E. Ostua, A. Millan, P. Ruiz-deClavijo, J. I. Villar, J. Quiros,
Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión, Proc. 9th Conference on Reconfigurable Computing and Applications (JCRA), Madrid, Spain, September 2009 [Full Paper (PDF)]
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J. Quiros, J. Viejo, A. Muñoz, A. Millan, E. Ostua and J. I. Villar,
Implementación sobre FPGA de un cliente SNTP usando MicroBlaze, Proc. 15th Iberchip Workshop (IWS), Iguazu Falls, Brazil, February 2010 [-Full Paper (PDF)]
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J. Viejo, J. I. Villar, J. Juan, A. Millan, M. J. Bellido, E. Ostua,
Design and implementation of a suitable core for on-chip long-term verification, Proc. 5th IEEE International Symposium on Industrial Embedded Systems (SIES), Trento, Italy, July 2010 [-Full Paper (PDF)]
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J. Viejo, J. I. Villar, J. Juan, A. Millan, M. J. Bellido, J. Quiros,
Verificación on-chip de larga duración de sistemas con eventos lógicos dispersos en el tiempo, Proc. 10th Jornadas de Computación Reconfigurable y Aplicaciones (JCRA), Valencia, Spain, September 2010 [-Full Paper (PDF)]
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J. Viejo, J. I. Villar, J. Juan, A. Millan, E. Ostua, J. Quiros,
Long-term on-chip verification of systems with logical events scattered in time, Proc. 25th Conference on Design of Circuits and Integrated Systems (DCIS), Lanzarote, Spain, November 2010 [-Full Paper (PDF)]
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J. Quiros, J. Viejo, A. Millan, A. Muñoz, J. I. Villar, D. Guerrero,
Implementation of a configuration server for a hardware SNTP synchronization platform based on FPGA, Proc. 7th Southern Conference on Programmable Logic (SPL), Cordoba, Argentina, April 2011 [Full Paper (PDF)]
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J. I. Villar, J. Juan, M. J. Bellido, J. Viejo, D. Guerrero, J. Decaluwe
Python as a Hardware Description Language: A Case Study, Proc. 7th Southern Conference on Programmable Logic (SPL), Cordoba, Argentina, April 2011 [Full Paper (PDF)]
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J. Ruiz, J. I. Villar, M. J. Bellido, D. Guerrero, J. Viejo, P. Ruiz-de-Clavijo, J. Juan
Diseño e implementación de un controlador domótico reconfigurable basado en hardware y software libre, Proc. 12th JCRA Workshop on Reconfigurable Computing and Applications, Elche, Spain, September 2012 [Full Paper (PDF)]
Other
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J. I. Villar, Advisor: J. Bellido,
Definición de una Metodología de Codiseño e Implementación de Sistemas Empotrados en un Chip con Hardware Libre, M.Eng Thesis, School of Computer Engineering, University of Seville, June 2008 [Full Paper (PDF)]